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            <idno type="stamp" n="LIRMM">Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier</idno>
            <idno type="stamp" n="SMARTIES" corresp="LIRMM">Smart Integrated Electronic Systems</idno>
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            <idno type="stamp" n="MIC">Département Microélectronique</idno>
            <idno type="stamp" n="MIPS">Mathématiques, Informatique, Physique et Systèmes</idno>
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                <title xml:lang="en">Direct digital synthesiser (DDS) design parameters optimisation for vibrating MEMS sensors: Optimisation of phase accumulator, Look-Up Table (LUT) and Digital to Analog Converter (DAC) sizes</title>
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                <title level="m">Symposium on Design, Test, Integration and Packaging of MEMS/MOEMS</title>
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                  <settlement>Cannes</settlement>
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                  <publisher>IEEE</publisher>
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                <term xml:lang="en">MEMS</term>
                <term xml:lang="en">Accelerometer</term>
                <term xml:lang="en">Inertial sensor</term>
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              <p>Onera has been developing quartz based MEMS inertial sensors for long, including for some years the associated digital electronics. Direct Digital Synthesis (DDS) and computerised control loops have been introduced as a replacement for self-sustained oscillators and analog PLL. However, the design parameters of digital synthesisers (word length of phase accumulator, size of Look Up Table, number of bits of DAC) affect the excitation signal spectrum driving the sensors. Spurious noise induced by those parameters can alter the sensors performances, especially in our cases of highly resonant vibrating structures (Q &gt; 100000): spurs close to the resonant frequency tend to lower the quality factor. This paper exposes a review of this spurious noise and an approach for optimising the DDS design parameters. In addition, alternate DDS structures are also investigated and compared to the classical phase accumulator / look up table / D-A converter structure. In one case, the DAC is only one bit wide, and the sine shape is obtained through large oversampling and low-pass filtering (Σ/Δ technique). In space designs, the ability to skip the DAC and remain fully digital inside a FPGA is a trade-off to be considered. In an other case, the output is only a square but with low jitter, reshaped by a narrow band pass filter, to generate the expected sine output. Here, the trade-off is towards simpler electronics (no memory table) with a slightly more sophisticated analog filter.</p>
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