The future of enterprise computing: Prepare for compute continuum, 2011. ,
CMOS reliability challenges the future of commercial digital electronics and nasa, 2010. ,
Cross-layer early reliability evaluation for the computing continuum official website, 2013. ,
A model for transient fault propagation in combinatorial logic, Proceedings of the 9th IEEE On-Line Testing Symposium, pp.111-115, 2003. ,
Techniques for transient fault sensitivity analysis and reduction in vlsi circuits, Proceedings of the 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp.597-604, 2003. ,
Impact of die-to-die and withindie parameter fluctuations on the maximum clock frequency distribution for gigascale integration, IEEE Journal of Solid-State Circuits, vol.37, pp.183-190, 2002. ,
Statistical timing analysis for intra-die process variations with spatial correlations, Proceedings of the International Conference on Computer Aided Design, pp.900-907, 2003. ,
Cost-effective approach for reducing soft error failure rate in logic circuits, Proceedings of the International Test Conference, vol.1, pp.893-901, 2003. ,
Accurate and efficient analysis of single event transients in vlsi circuits, Proceedings of the 9th IEEE On-Line Testing Symposium, pp.101-105, 2003. ,
Modeling the effect of technology trends on the soft error rate of combinational logic, Proceedings of the International Conference on Dependable Systems and Networks, pp.389-398, 2002. ,
A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor, pp.29-42, 2003. ,
Softarch: An architecture level tool for modeling and analyzing soft errors, Proceedings of the International Conference on Dependable Systems and Networks, 2005. DSN 2005, pp.496-505, 2005. ,
Examining ace analysis reliability estimates using fault-injection, pp.460-469, 2007. ,
Mechanisms for bounding vulnerabilities of processor structures, Proceedings of the 34th Annual International Symposium on Computer Architecture, pp.506-515, 2007. ,
Dynamic prediction of architectural vulnerability from microarchitectural state, Proceedings of the 34th Annual International Symposium on Computer Architecture, pp.516-527, 2007. ,
Versatile prediction and fast estimation of architectural vulnerability factor from processor performance metrics, Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture, pp.129-140, 2009. ,
Quantized AVF: A means of capturing vulnerability variations over small windows of time, 2009. ,
Characterizing microarchitecture soft error vulnerability phase behavior, Proceedings of the 14th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems, pp.147-155, 2006. ,
Computing architectural vulnerability factors for addressbased structures, Proceedings of the 32Nd Annual International Symposium on Computer Architecture 2005. ISCA 2005, pp.532-543, 2005. ,
Accurate and simplified prediction of avf for delay and energy efficient cache design, J. Comput. Sci. Technol, vol.26, issue.3, pp.504-519, 2011. ,
Accurate vulnerability estimation for cache hierarchy, Proceedings of the 7th International Conference on Networked Computing and Advanced Information Management 2011. NCM, pp.7-14, 2001. ,
Online estimation of architectural vulnerability factor for soft errors, Proceedings of the 35th International Symposium on Computer Architecture, pp.341-352, 2008. ,
The case for lifetime reliability-aware microprocessors, Proceedings of the 31st Annual International Symposium on Computer Architecture, vol.32, p.276, 2004. ,
A framework for architecture-level lifetime reliability modeling, Proceedings of the 37th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, pp.534-543, 2007. ,
Power and reliability management of socs, IEEE Trans. VLSI Syst, vol.15, issue.4, pp.391-403, 2007. ,
Agesim: A simulation framework for evaluating the lifetime reliability of processor-based socs, Proceedings of the Design, Automation, and Test in Europe Conference 2010. DATE 2010, pp.51-56, 2010. ,
Impact of parameter variations on multicore architectures, Workshop on Architectural Support for Gigascale Integration (ASGI-06, 2006. ,
Quantifying the impact of process variability on uniprocessor behavior, Workshop on Architectural Reliability, 2006. ,
Statistics of extremes, with applications in environment, insurance, and finance, Monographs on Statistics and Applied Probability, vol.99, pp.1-78, 2004. ,
Evaluating the effects of compiler optimisations on AVF, Proceedings of the Workshop on interaction between compilers and computer architecture, 2008. ,
Eliminating microarchitectural dependency from architectural vulnerability, Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture, pp.117-128, 2009. ,
Dynamic dead-instruction detection and elimination, Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems, pp.199-210, 2002. ,
Static analysis of seu effects on software applications, Proceedings of the International Test Conference, pp.500-508, 2002. ,
Using pvf traces to accelerate avf modeling, Proceedings of the IEEE Workshop on Silicon Errors in Logic-System Effects, pp.23-24, 2010. ,
Statistical reliability estimation of microprocessor-based systems, IEEE Trans. Computers, vol.61, issue.11, pp.1521-1534, 2012. ,
The effect of input data on program vulnerability, Workshop on System Effects of Logic Soft Errors, 2009. ,
Characterizing the effects of transient faults on a high-performance processor pipeline, Proceedings of the International Conference on Dependable Systems and Networks, pp.61-70, 2004. ,
An experimental study of soft errors in microprocessors, IEEE Micro, vol.25, issue.6, pp.30-39, 2005. ,
Characterization of error-tolerant applications when protecting control data, Proceedings of the IEEE International Symposium on Workload Characterization, pp.142-149, 2006. ,
A field analysis of system-level effects of soft errors occurring in microprocessors used in information systems, Proceedings of the IEEE International Test Conference, pp.1-10, 2008. ,
Stealth works: Emulating memory errors, Proceedings of the First International Conference on Runtime Verification, RV'10, pp.360-367, 2010. ,
IVF: Characterizing the vulnerability of microprocessor structures to intermittent faults, IEEE Transactions on Very Large Scale Integration (VLSI), vol.20, pp.777-790, 2012. ,
Susceptibility of commodity systems and software to memory soft errors, IEEE Trans. Computers, vol.53, issue.12, pp.1557-1568, 2004. ,
Multi-media applications and imprecise computation, Proceedings of the 8th Euromicro Conference on Digital System Design, pp.2-7, 2005. ,
Application-level correctness and its impact on fault tolerance, Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, pp.181-192, 2007. ,
ERSA: Error resilient system architecture for probabilistic applications, Proceedings of the Design, Automation Test in Europe Conference Exhibition 2010. DATE 2010, pp.1560-1565, 2010. ,
Perturbation-based fault screening, Proceedings of the IEEE 13th International Symposium on High Performance Computer Architecture, pp.169-180, 2007. ,
Restore: Symptom-based soft error detection in microprocessors, IEEE Trans. Dependable Sec. Comput, vol.3, issue.3, pp.188-201, 2006. ,
Swat: An error resilient system, 4th Workshop on Silicon Errors in Logic -System Effects (SELSE -IV), 2008. ,