OAP: An obstruction-aware cache management policy for STT-RAM last-level caches, Proc. of Design, Automation Test in Europe Conference Exhibition (DATE), pp.847-852, 2013. ,
Phase-change random access memory: A scalable technology, IBM Journal of Research and Development, vol.52, issue.4, pp.465-479, 2008. ,
Memristive devices for stochastic computing, Proc. of IEEE International Symposium onCircuits and Systems (ISCAS), pp.2592-2595, 2014. ,
The emergence of spin electronics in data storage, Nature Materials, vol.6, issue.11, pp.813-823, 2007. ,
Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity, Acta Materialia, vol.61, issue.3, pp.952-973, 2013. ,
NVSim: A circuit-level performance, energy, and area model for emerging nonvolatile memory, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.7, pp.994-1007, 2012. ,
CACTI 6.0: A tool to understand large caches, 2009. ,
A novel nonvolatile memory with spin torque transfer magnetization switching: Spin-RAM, Proc. of IEEE International Electron Devices Meeting (IEDM), pp.459-462, 2005. ,
On-axis scheme and novel MTJ structure for sub30nm Gb density STT-MRAM, Proc. of IEEE International Electron Devices Meeting (IEDM), 2010. ,
Extended scalability of perpendicular STT-MRAM towards sub-20nm MTJ node, Proc. of IEEE International Electron Devices Meeting (IEDM), 2011. ,
DFSTT-MRAM: Dual Functional STT-MRAM Cell Structure for Reliability Enhancement and 3-D MLC Functionality, IEEE Transactions on Magnetics, vol.50, issue.6, 2014. ,
A novel architecture of the 3D stacked MRAM L2 cache for CMPs, Proc. of IEEE International Symposium on High Performance Computer Architecture (HPCA), pp.239-249, 2009. ,
Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design, Proc. of IEEE International Solid-State and Integrated Circuit Technology (ICSICT), 2014. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01248593
Technology Comparison for Large Last-Level Caches (L 3 Cs): Low-Leakage SRAM, Low Write-Energy STT-RAM, and Refresh-Optimized eDRAM, Proc. of IEEE International Symposium on High Performance Computer Architecture (HPCA), pp.143-154, 2013. ,
Lower-bits cache for low power STT-RAM caches, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), pp.480-483, 2012. ,
Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses, Microelectronics Reliability, vol.54, pp.1774-1778, 2014. ,
URL : https://hal.archives-ouvertes.fr/hal-01216431
A novel sensing circuit for deep submicron spin transfer torque MRAM (STT-MRAM), IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, issue.1, pp.181-186, 2012. ,
High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits, IEEE Transactions on Magnetics, vol.45, issue.10, pp.3784-3787, 2009. ,