A body-biasing of readout circuit for STT-RAM with improved thermal reliability

Abstract : As the integration density rockets up for contemporary VLSI circuits, power consumption limits the scalability of technology advancement of CMOS. Spin transfer torque-magnetic random access memory (STT-MRAM), as one of the emerging non-CMOS technologies, has the promising prospect of low standby power, fast access speed and compatibility with the CMOS fabrication process. However, with the technology node scaling down, typical 1 Transistor-1 Magnetic Tunnel Junction (1T-1MTJ) STT-RAM cell suffers from severe reliability challenges, especially for read operation under temperature fluctuation. In this paper, we quantitatively analyze the temperature effect on read reliability of STT-RAM cell and propose a novel body-biasing feedback readout circuit design to improve the read sensing margin under different temperatures. The experiments based on 40nm CMOS technology and MTJ compact model validate the effectiveness of the proposed method. The improved sensing margin also permits a smaller sensing current for reading such that higher read energy efficiency can be achieved.
Type de document :
Communication dans un congrès
ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.1530-1533, 2015, 〈10.1109/ISCAS.2015.7168937〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01248587
Contributeur : Aida Todri-Sanial <>
Soumis le : dimanche 27 décembre 2015 - 21:41:19
Dernière modification le : jeudi 24 mai 2018 - 15:59:25

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Lun Yang, Yuanqing Cheng, Yuhao Wang, Hao Yu, Weisheng Zhao, et al.. A body-biasing of readout circuit for STT-RAM with improved thermal reliability. ISCAS: International Symposium on Circuits and Systems, May 2015, Lisbon, Portugal. pp.1530-1533, 2015, 〈10.1109/ISCAS.2015.7168937〉. 〈lirmm-01248587〉

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