Systematic defects in deep sub-micron technologies, IEEE International Test Conference, pp.290-299, 2005. ,
Towards a World Without Test Escapes, IEEE International Test Conference, 2008. ,
Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs, IEEE International Test Conference, 2009. ,
Cell-aware Production test results from a 32-nm notebook processor, International Test Conference, pp.1-9, 2012. ,
Efficient and Accurate Method for Intragate Defect Diagnoses in Nanometer Technology and Volume Data'', Design, Automation & Test in Europe Conference & Exhibition, 2009. DATE '09, pp.988-993 ,
Effect-Cause Intra-Cell Diagnosis at Transistor Level, 14th International Symposium & Exhibits on Quality Electronic Design, pp.476-483, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00817224
A Deductive Method for Simulating Faults in Logic Circuits, IEEE Transaction on Computer, vol.5, pp.464-471, 1972. ,
Diagnosis of Resistive-Open and Stuck-Open Defects in Digital CMOS ICs, IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems, vol.24, issue.11, pp.1748-1759, 2005. ,
LIFTING: a Flexible Open-Source Fault Simulator, IEEE Asian Test Symposium, pp.35-40, 2008. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00343610
An efficient fault simulation technique for transition faults in non-scan sequential circuits, pp.50-55, 2009. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00371197
A pattern ordering algorithm for reducing the size of fault dictionaries, IEEE VLSI Test Symposium, 2006. ,