On hierarchical statistical static timing analysis, Design, Automation Test in Europe Conference Exhibition, pp.1320-1325, 2009. ,
Small-delay defects detection under process variation using Inter-Path Correlation, VLSI Test Symposium (VTS), pp.127-132, 2012. ,
Path-RO: A novel on-chip critical path delay measurement under process variations, ComputerAided Design, pp.640-646, 2008. ,
Small-Delay Defect Detection in the Presence of Process Variations, Quality Electronic Design, 2007. ISQED '07. 8th International Symposium on, pp.711-716, 2007. ,
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis, Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, pp.829-834, 2007. ,
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation, IEEE Transactions on VLSI Systems, pp.958-970, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806774
The combined effect of process variations and power supply noise on clock skew and jitter, Quality Electronic Design (ISQED), pp.320-327, 2012. ,
Highquality pattern selection for screening small-delay defects considering process variations and crosstalk, Design, Automation Test in Europe Conference Exhibition (DATE), pp.1426-1431, 2010. ,
A general probabilistic framework for worst case timing analysis, Design Automation Conference, pp.556-561, 2002. ,
Principles of cmos vlsi design: A systems perspective, 1993. ,
Equivalent Elmore delay for RLC trees, Design Automation Conference, pp.715-720, 1999. ,
, Predictive Technology Model (PTM)
Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations, Custom Integrated Circuits Conference, pp.309-312, 2005. ,
, ITC'99 Benchmark circuits, 2003.
Path Delay Test in the Presence of MultiAggressor Crosstalk, Power Supply Noise and Ground Bounce, Design and Diagnostics of Electronic Circuits and Systems,. 17th, 2014. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01248599