TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test, IEEE International Reliability Physics Symposium (IRPS), 2012. ,
Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers, European Test Symposium (ETS), pp.1-6, 2013. ,
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs, IEEE International Conference on Computer Design (ICCD), pp.70-77, 2009. ,
A DfT Architecture for 3D-SICs Based on a Standardizable Die Wrapper, ACM Journal of Electronic Testing: Theory and Applications (JETTA), vol.28, pp.73-92, 2012. ,
Self-Test Methodology and Structures for Pre-Bond TSV Testing in 3D-IC System, IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.393-396, 2012. ,
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs, IEEE VLSI Test Symposium (VTS), pp.20-25, 2011. ,
3D-IC interconnect test, diagnosis, and repair, IEEE VLSI Test Symposium (VTS), pp.118-123, 2013. ,
Chou Post-bond test techniques for TSVs with crosstalk faults in 3D ICs, IEEE International Symposium on VLSI Design Automation and Test (VLSI-DAT), pp.1-4, 2012. ,
, Small delay testing for TSVs in 3-D ICs, in Design Automation Conference (DAC), pp.1031-1036, 2012.
Comparing Through-Silicon-Via (TSV) Void/Pinhole Defect Self-Test Methods, ACM Journal of Electronic Testing: Theory and Applications (JETTA), vol.28, pp.27-38, 2012. ,
TSV Open Defects in 3D Integrated Circuits: Characterization, Test and Optimal Spare Allocation, Design Automation Conference (DAC), pp.1024-1030, 2012. ,
Design and Testing Strategies for Modular 3-DMultiprocessor Systems Using Die-Level Through Silicon Via Technology, IEEE Journal in Emerging and Selected Topics in Circuits and Systems (JETCAS), vol.2, pp.295-306, 2012. ,
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC, Design Automation Conference (DAC), pp.783-788, 2011. ,
Buffer delay change in the presence of power and ground noise, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.11, pp.461-473, 2003. ,
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Pattern Generation, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.21, pp.958-970, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806774
Resistive-Open Defect Analysis for Through-SiliconVias, IEEE European Test Symposium (ETS), pp.183-183, 2012. ,
Vectorless Analysis of Supply Noise Induced Delay Variation, IEEE International Conference Computer Aided Design, pp.184-191, 2003. ,
Static Timing Analysis Considering Power Supply Variations, IEEE International Conference Computer Aided Design, pp.365-371, 2005. ,
Good Resampling Methods: A Practical Guide to Data Analysis Birkhauser, 2006. ,
Identification of Gaussian mixture model using Mean Variance Mapping Optimization: Venezuelan case, IEEE PES International Conference and Exhibition on Innovative Smart Grid Technologies (ISGT Europe), pp.1-6, 2012. ,
Process and RF modeling of TSV last approach for 3D RF interposer, IEEE International Interconnect Technology Conference and Materials for Advanced Metalization (IITC/MAM), pp.1-3, 2011. ,