A novel method to mitigate TSV electromigration for 3D ICs
Résumé
Three-dimensional (3D) integration is considered to be a promising technology to tackle the global interconnect scaling problem for tera-scale integrated circuits (ICs). 3D ICs typically employ through-silicon-vias (TSVs) to connect planar circuits vertically. Due to its immature fabrication process, several defects such as void, misalignment and dust contamination, may be introduced. These defects can increase current densities within TSVs significantly and cause severe electromigration (EM) effect, which can degrade the reliability of 3D ICs considerably. In this paper, we propose a novel method to mitigate EM effect of the defective TSV. At first, we analyze various possible TSV defects and demonstrate that they can aggravate electromigration dramatically. Based on the observation that EM effect can be alleviated significantly by balancing the direction of current flow within TSV, we design an on-line self-healing circuit to protect defective TSVs, which can be detected during test procedure, from EM without degrading performance. Experimental results show that our proposed method can achieve tens times improvement on mean time to failure (MTTF) compared to the design without using such method with negligible hardware overheads and power consumption.
Mots clés
Bonding
Analytical models
void
through-silicon-vias
three-dimensional integration
tera-scale integrated circuits
power consumption
planar circuits
online self-healing circuit
misalignment
mean time to failure
hardware overheads
global interconnect scaling problem
fabrication process
dust contamination
defective TSV
current flow direction
current densities
TSV electromigration
EM effect
3D IC reliability
three-dimensional integrated circuits
integrated circuit reliability
integrated circuit interconnections
electromigration
current density
Metals
Reliability engineering
Through-silicon vias
Very large scale integration