M. Renaudin, J. Rigaud, and . Baptiste, Etat de lart sur la conception des circuits asynchrones: perspectives pour lintégration des systèmes complexes, 2000.

P. Vivet, Une méthodologie de conception de circuits intégrés quasi-insensibles aux délais: applicationàapplication`applicationà l'´ etude etàet`età la réalisation d'un processeur RISC 16-bit asynchrone, 2001.

M. Moreira, . Trevisan, N. L. Calazans, and . Vilar, Proposal of an Exploration of Asynchronous Circuits Templates and their Applications, 2014.

M. Jeitler and J. Lechner, Comparing the robustness of synchronous and asynchronous circuits by fault injection [5] Muttersbach, Jens and Villiger, Thomas and Fichtner, Wolfgang, Practical design of globally-asynchronous locally-synchronous systems, Advanced Research in Asynchronous Circuits and Systems, ASYNC 2000) Proceedings. Sixth International Symposium on, pp.52-95, 2000.

P. Teehan, M. Greenstreet, and G. Lemieux, A survey and taxonomy of GALS design styles, Design & Test of Computers, pp.418-428, 2007.

P. Roche, J. Autran, G. Gasiot, and D. Munteanu, Technology downscaling worsening radiation effects in bulk: SOI to the rescue, Nuclear Science, IEEE international electron device meeting (IEDM2013), pp.766-769

P. Flatresse, G. Bastien, J. Noel, . Pelloux-prayer, . Bertrand et al., Franck and Planes, Nicolas and others, Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.424-425, 2013.

W. Kang, . Zhao, . Weisheng, . Wang, . Zhaohao et al., An overview of spin-based integrated circuits, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.676-683, 2014.
DOI : 10.1109/ASPDAC.2014.6742969

D. Pendina and G. , Conception innovante et développement d'outils de conception d'ASIC pour Technologie Hybride CMOS/Magnétique, 2012.

Y. Conraux, Préparation et caractérisation d'un alliage amorphe ferrimagnétique de GdCo entrant dans la conception de jonctions tunnel magnétiques Résistance des jonctions tunnel magnétiques aux rayonnements ionisants, Ph.D, 2005.

R. C. Sousa, I. Prejbeanu, and . Lucian, Non-volatile magnetic random access memories (MRAM), Comptes Rendus Physique, vol.6, issue.9, pp.1013-1021, 2005.
DOI : 10.1016/j.crhy.2005.10.007

B. Dieny, . Sousa, . Herault, C. Papusoi, . Prenat et al., Spin-transfer effect and its use in spintronic components, International Journal of Nanotechnology, vol.7, issue.4/5/6/7/8, pp.591-614, 2010.
DOI : 10.1504/IJNT.2010.031735

K. Jabeur, . Buda-prejbeanu, . Ld, G. Prenat, D. Pendina et al., Study of two writing schemes for a magnetic tunnel junction based on spin orbit torque, International Journal of Electronics Science and Engineering, vol.7, issue.8, pp.501-507, 2013.

J. Di, A framework on mitigating single event upset using delayinsensitive asynchronous circuits, Region 5 Technical Conference, pp.354-357, 2007.

R. Gong, C. , W. Liu, . Fang, . Dai et al., A New Approach to Single Event Effect Tolerance Based on Asynchronous Circuit Technique, Journal of Electronic Testing, vol.32, issue.6, pp.1-3, 2008.
DOI : 10.1007/s10836-007-5029-z

C. Bolchini, A. Miele, . Rebaudengo, . Maurizio, F. Salice et al., Software and Hardware Techniques for SEU Detection in IP Processors, Journal of Electronic Testing, vol.49, issue.3, pp.1-335, 2008.
DOI : 10.1007/s10836-007-5028-0

O. Goncalves, Conception sur mesure d'un FPGA durci aux radiations base de mmoires magntiques, 2013.

P. Peronnard, Méthodes et outils pour l'´ evaluation de la sensibilité de circuits intégrés avancés face aux radiations naturelles, 2009.

C. Robert and . Baumann, Soft Errors in Advanced Semiconductor Devices - Part I: The Three Radiation Sources, Device and Materials reliability, IEEE Transactions on, vol.1, issue.1, pp.17-22, 2001.

W. Zhao, . Deng, . Erya, J. Klein, and C. , Yuanqing and Ravelosona, Dafiné and others, A radiation hardened hybrid spintronic/CMOS nonvolatile unit using magnetic tunnel junctions, Journal of Physics D: Applied Physics, vol.47, issue.40, p.405003, 2014.

. Ferlet-cavrois, . Paillet, . Gaillardin, . Lambert, . Baggio et al., Statistical analysis of the charge collected in SOI and bulk devices under heavy lon and proton irradiationImplications for digital SETs, Nuclear Science, IEEE Transactions on, vol.53, issue.6, pp.3242-3252, 2006.

R. Brum, Une tude des mmoires magnetiques appliques aux processeurs et FPGAs, 2014.

E. Zianbetov, E. Beigne, D. Pendina, and G. , Non-volatility for Ultra-Low Power Asynchronous Circuits in Hybrid CMOS/Magnetic Technology, 2015 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015.
DOI : 10.1109/ASYNC.2015.27