A 4-Mb toggle MRAM based on a novel bit and switching method, IEEE Transactions on Magnetics, 2005. ,
DOI : 10.1109/TMAG.2004.840847
Erratum: Basic principles of STT-MRAM cell operation in memory arrays, Journal of Physics D: Applied Physics, vol.46, issue.13, 2013. ,
DOI : 10.1088/0022-3727/46/13/139601
Thermally assisted MRAM, Journal of Physics: Condensed Matter, 2007. ,
DOI : 10.1088/0953-8984/19/16/165218
The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011. ,
DOI : 10.1145/2024716.2024718
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.7, pp.994-1007, 2012. ,
DOI : 10.1007/978-1-4419-9551-3_2
OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp.847-852, 2013. ,
DOI : 10.7873/DATE.2013.179
Architectural aspects in design and analysis of SOT-based memories, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.700-707, 2014. ,
DOI : 10.1109/ASPDAC.2014.6742972
Fine-Grain Power-Gating on STT-MRAM Peripheral Circuits with Locality-aware Access Control, The Memory Forum (in conjounction with the 41 st International Symposium on Computer Architecture), 2014. ,
A Comparative Study of STT-MTJ based Non-Volatile Flip-Flops, Circuits and Systems (ISCAS), IEEE International Symposium on, pp.109-112, 2013. ,
Design and fabrication of a perpendicular MTJ based nonvolatile programmable switch achieving 40% less area using shared-control transistor structure, Journal of Applied Physics, vol.115, pp.17-742, 2014. ,
Programmable logic using giant-magnetoresistance and spin-dependent tunneling devices (invited), Journal of Applied Physics, vol.87, issue.9, pp.6674-6679, 2000. ,
DOI : 10.1063/1.372806
High speed, high stability and low power sensing amplifier for mtj/cmos hybrid logic circuits, 2009. ,
A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.317-320, 2013. ,
DOI : 10.1109/ASSCC.2013.6691046
Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions, IEEE Transactions on Magnetics, vol.51, issue.2 ,
DOI : 10.1109/TMAG.2014.2347009
URL : https://hal.archives-ouvertes.fr/lirmm-01284619
Match In Place. A novel way to perform secure and fast user's authentication, " available online at www.crocus-technology ,