STT-MRAM cuts power use by 80%, eetimes.com ,
NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.7, pp.994-1007, 2012. ,
DOI : 10.1007/978-1-4419-9551-3_2
Cacti 6.0: A tool to model large caches, Published in International Symposium on Microarchitecture, 2007. ,
The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011. ,
DOI : 10.1145/2024716.2024718
Accuracy evaluation of GEM5 simulator system, 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), pp.1-7 ,
DOI : 10.1109/ReCoSoC.2012.6322869
PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors, 2008 IEEE International Symposium on Workload Characterization, pp.47-56, 2008. ,
DOI : 10.1109/IISWC.2008.4636090
Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.554-559, 2008. ,
DOI : 10.1145/1391469.1391610
Hybrid cache architecture with disparate memory technologies, ACM SIGARCH Computer Architecture News, pp.34-45, 2009. ,
Energy reduction for stt-ram using early write termination, International Conference on Computer-Aided Design, pp.264-268, 2009. ,
A novel architecture of the 3D stacked MRAM L2 cache for CMPs, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.239-249, 2009. ,
DOI : 10.1109/HPCA.2009.4798259
Match In Place. A novel way to perform secure and fast user's authentication, " available online at www.crocus-technology ,