X. Wang, M. Tehranipoor, and J. Plusquellic, Detecting malicious inclusions in secure hardware: challenges and solutions, IEEE International Workshop on Hardware-Oriented Security and Trust (HOST'08), pp.15-19, 2008.

U. Guin, K. Huang, D. Dimase, J. M. Carulli, M. Tehranipoor et al., Counterfeit Integrated Circuits: A Rising Threat in the Global Semiconductor Supply Chain, Proceedings of the IEEE, pp.1207-1228, 2014.
DOI : 10.1109/JPROC.2014.2332291

M. Tehranipoor and F. Koushanfar, A Survey of Hardware Trojan Taxonomy and Detection, IEEE Design & Test of Computers, vol.27, issue.1, pp.10-25, 2010.
DOI : 10.1109/MDT.2010.7

S. Bhunia, M. S. Hsiao, M. Banga, and S. Narasimhan, Hardware Trojan Attacks: Threat Analysis and Countermeasures, Proceedings of the IEEE, vol.102, issue.8, pp.1229-1247, 2014.
DOI : 10.1109/JPROC.2014.2334493

J. Rajendran, O. Sinanoglu, and R. Karri, Regaining Trust in VLSI Design: Design-for-Trust Techniques, Proceedings of the IEEE, pp.1266-1282, 2014.
DOI : 10.1109/JPROC.2014.2332154

D. Agrawal, S. Baktir, D. Karakoyunlu, P. Rohatgi, and B. Sunar, Trojan Detection using IC Fingerprinting, 2007 IEEE Symposium on Security and Privacy (SP '07), pp.296-310, 2007.
DOI : 10.1109/SP.2007.36

Y. Jin and Y. Makris, Hardware trojan detection using path delay fingerprint, IEEE International Workshop on Hardware- Oriented Security and Trust (HOST'08), pp.51-57, 2008.

F. Wolf, C. Papachristou, S. Bhunia, and R. S. Chakraborty, Towards trojan-free trusted ICs, Proceedings of the conference on Design, automation and test in Europe, DATE '08, pp.1362-1365, 2008.
DOI : 10.1145/1403375.1403703

R. S. Chakraborty, F. Wolff, S. Paul, C. Papachristou, and S. Bhunia, MERO: A Statistical Approach for Hardware Trojan Detection, International Conference on Cryptographic Hardware and Embedded Systems (CHES'09), pp.396-410, 2009.
DOI : 10.1007/978-3-642-04138-9_28

S. Dupuis, P. Ba, M. Flottes, G. D. Natale, and B. Rouzeyre, New Testing Procedure for Finding Insertion Sites of Stealthy Hardware Trojans, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.776-781, 2015.
DOI : 10.7873/DATE.2015.1102

URL : https://hal.archives-ouvertes.fr/lirmm-01141619

P. Kitsos, D. E. Simos, J. Torres-jimenez, and A. G. Voyiatzis, Exciting FPGA cryptographic Trojans using combinatorial testing, 2015 IEEE 26th International Symposium on Software Reliability Engineering (ISSRE), 2015.
DOI : 10.1109/ISSRE.2015.7381800

K. Xiao and M. Tehranipoor, BISA: Built-in self-authentication for preventing hardware Trojan insertion, 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp.45-50, 2013.
DOI : 10.1109/HST.2013.6581564

P. Ba, P. Manikandan, S. Dupuis, M. Flottes, G. D. Natale et al., Hardware Trojan prevention using layout-level design approach, 2015 European Conference on Circuit Theory and Design (ECCTD), 2015.
DOI : 10.1109/ECCTD.2015.7300093

URL : https://hal.archives-ouvertes.fr/lirmm-01234072

R. S. Chakraborty, S. Paul, and S. Bhunia, On-demand transparency for improving hardware Trojan detectability, 2008 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.48-50, 2008.
DOI : 10.1109/HST.2008.4559048

R. S. Chakraborty and S. Bhunia, Security Against Hardware Trojan Attacks Using Key-Based Design Obfuscation, Journal of Electronic Testing, vol.3200, issue.3, pp.767-785, 2011.
DOI : 10.1007/s10836-011-5255-2

H. Salmani, M. Tehranipoor, and J. Plusquellic, A Novel Technique for Improving Hardware Trojan Detection and Reducing Trojan Activation Time, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp.112-125, 2012.
DOI : 10.1109/TVLSI.2010.2093547

S. Dupuis, P. Ba, G. D. Natale, M. Flottes, and B. Rouzeyre, A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans, 2014 IEEE 20th International On-Line Testing Symposium (IOLTS), 2014.
DOI : 10.1109/IOLTS.2014.6873671

URL : https://hal.archives-ouvertes.fr/lirmm-01025275

M. Banga and M. S. Hsiao, VITAMIN: Voltage inversion technique to ascertain malicious insertions in ICs, 2009 IEEE International Workshop on Hardware-Oriented Security and Trust, pp.104-107, 2009.
DOI : 10.1109/HST.2009.5224960

W. Danesh, J. Dofe, and Q. Yu, Efficient Hardware Trojan Detection with Differential Cascade Voltage Switch Logic, VLSI Desing, Special Issue on Advanced VLSI Architecture Design for Emerging Digital Systems, 2014.
DOI : 10.1109/TIFS.2010.2096811

Y. Alkabani, Trojan Immune Circuits Using Duality, 2012 15th Euromicro Conference on Digital System Design, pp.177-184, 2012.
DOI : 10.1109/DSD.2012.134

J. Ichimiya, Layout design method of semiconductor integrated circuit, and semiconductor integrated circuit, with high integration level of multiple level metalization, US Patent, vol.7, p.76756, 2006.

S. Bhasin, J. Danger, X. T. Ngo, and S. Guilley, Hardware Trojan Horses in Cryptographic IP Cores, 2013 Workshop on Fault Diagnosis and Tolerance in Cryptography, pp.15-29, 2013.
DOI : 10.1109/FDTC.2013.15

URL : https://hal.archives-ouvertes.fr/hal-00855146