I. Koren and C. Krishna, Fault Tolerant Systems, 2007.

R. E. Lyons and W. Vanderkulk, The Use of Triple-Modular Redundancy to Improve Computer Reliability, IBM Journal of Research and Development, vol.6, issue.2, pp.200-209, 1962.
DOI : 10.1147/rd.62.0200

J. Vial, A. Bosio, P. Girard, C. Landrault, S. Pravossoudovitch et al., Using TMR Architectures for Yield Improvement, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.7-15, 2008.
DOI : 10.1109/DFT.2008.23

URL : https://hal.archives-ouvertes.fr/lirmm-00406967

J. Vial, A. Virazel, A. Bosio, P. Girard, C. Landrault et al., Is triple modular redundancy suitable for yield improvement?, IET Computers & Digital Techniques, vol.3, issue.6, pp.581-592, 2009.
DOI : 10.1049/iet-cdt.2008.0127

M. Zhang, Sequential Element Design With Built-In Soft Error Resilience, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.14, issue.12, pp.1368-1378, 2006.
DOI : 10.1109/TVLSI.2006.887832

D. Ernst, Razor: a low-power pipeline based on circuit-level timing speculation, 22nd Digital Avionics Systems Conference. Proceedings (Cat. No.03CH37449), pp.7-18, 2003.
DOI : 10.1109/MICRO.2003.1253179

S. Das, RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance, IEEE Journal of Solid-State Circuits, vol.44, issue.1, pp.32-48, 2009.
DOI : 10.1109/JSSC.2008.2007145

M. E. Imhof and H. Wunderlich, Soft error correction in embedded storage elements, 2011 IEEE 17th International On-Line Testing Symposium, pp.169-174, 2011.
DOI : 10.1109/IOLTS.2011.5993832

J. Yao, DARA: A Low-Cost Reliable Architecture Based on Unhardened Devices and Its Case Study of Radiation Stress Test, IEEE Transactions on Nuclear Science, vol.59, issue.6, pp.2852-2858, 2012.

V. Subramanian and A. K. Somani, Conjoined Pipeline: Enhancing Hardware Reliability and Performance through Organized Pipeline Redundancy, 2008 14th IEEE Pacific Rim International Symposium on Dependable Computing, pp.9-16, 2008.
DOI : 10.1109/PRDC.2008.54

M. Mehrara, M. Attariyan, S. Shyam, K. Constantinides, V. Bertacco et al., Low-Cost Protection for SER Upsets and Silicon Defects, 2007 Design, Automation & Test in Europe Conference & Exhibition, pp.1-6, 2007.
DOI : 10.1109/DATE.2007.364449

A. Benso, A. , and P. Prinetto, Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, 2003.
DOI : 10.1007/b105828

D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard et al., A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits, 2011 Asian Test Symposium, pp.136-141, 2011.
DOI : 10.1109/ATS.2011.89

URL : https://hal.archives-ouvertes.fr/lirmm-00679513

I. Wali, A. Virazel, A. Bosio, L. Dilillo, and P. Girard, An Effective Hybrid Fault-Tolerant Architecture for Pipeline Cores, IEEE European Test Symposium, pp.1-6, 2015.

I. Wali, A. Virazel, A. Bosio, P. Girard, and M. S. Reorda, Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture, 2015 IEEE 21st International On-Line Testing Symposium (IOLTS), 2015.
DOI : 10.1109/IOLTS.2015.7229838

URL : https://hal.archives-ouvertes.fr/lirmm-01272735

P. Liden, P. Dahlgren, R. Johansson, and J. Karlsson, On latching probability of particle induced transients in combinational networks, Proceedings of IEEE 24th International Symposium on Fault- Tolerant Computing, pp.340-349, 1994.
DOI : 10.1109/FTCS.1994.315626

. Alvisi, Modeling the effect of technology trends on the soft error rate of combinational logic, Int. Conf. on Dependable Systems and Networks, pp.389-398, 2002.

J. Velamala, R. Livolsi, M. Torres, and C. Yu, Design sensitivity of single event transients in scaled logic circuits, Proceedings of the 48th Design Automation Conference on, DAC '11, pp.694-699, 2011.
DOI : 10.1145/2024724.2024881

P. K. Lala, Self-Checking and Fault-Tolerant Digital Design, 2000.

D. A. Tran, A. Virazel, A. Bosio, L. Dilillo, P. Girard et al., A pseudo-dynamic comparator for error detection in fault tolerant architectures, 2012 IEEE 30th VLSI Test Symposium (VTS), pp.50-55, 2012.
DOI : 10.1109/VTS.2012.6231079

URL : https://hal.archives-ouvertes.fr/lirmm-00806778

G. Wirth, L. Kastensmidt, I. Fernanda, and . Ribeiro, Single Event Transients in Logic Circuits—Load and Propagation Induced Pulse Broadening, IEEE Transactions on Nuclear Science, vol.55, issue.6, pp.2928-2935, 2008.
DOI : 10.1109/TNS.2008.2006265

J. A. Blome, S. Feng, S. Gupta, and S. Mahlke, Online timing analysis for wearout detection, Proc. of the 2nd Workshop on Ar-chitectural Reliability, pp.51-60, 2006.