A. Ahari, H. Asadi, B. Khaleghi, and M. B. Tahoori, A power-efficient reconfigurable architecture using PCM configuration technology, Conference on Design, Automation & Test in Europe. European Design and Automation Association, p.336, 2014.
DOI : 10.7873/date2014.349

S. Ando, J. Fujita, S. Ito, Y. Yuasa, Y. Suzuki et al., Spin-transfer torque magnetoresistive random-access memory technologies for normally off computing (invited), Journal of Applied Physics, vol.115, issue.17, pp.17-172607, 2014.
DOI : 10.1063/1.4869828

T. W. Andre, J. J. Nahas, C. K. Subramanian, B. J. Garni, H. S. Lin et al., A 4-Mb 0.18-?m 1T1MTJ toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers, IEEE J. Solid-State Circ, vol.40, pp.1-301, 2005.

J. Borgeson, S. Shauer, and H. Diewald, Benchmarking MCU power consumption for ultra-low-power applications, 2012.

D. Chabi, W. Zhao, E. Deng, Y. Zhang, N. Ben-romdhane et al., Ultra Low Power Magnetic Flip-Flop Based on Checkpointing/Power Gating and Self-Enable Mechanisms, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, issue.6, pp.6-1755, 2014.
DOI : 10.1109/TCSI.2013.2295026

J. Choi, C. Jung, and K. Min, PCRAM Flip-Flop Circuits with Sequential Sleep-in Control Scheme and Selective Write Latch, JSTS:Journal of Semiconductor Technology and Science, vol.13, issue.1, pp.1-58, 2013.
DOI : 10.5573/JSTS.2013.13.1.058

L. Crippa, R. Micheloni, I. Motta, and M. Sangalli, Nonvolatile Memories: NOR vs. NAND Architectures, Memories in Wireless Systems, pp.29-53, 2008.
DOI : 10.1007/978-3-540-79078-5_2

. Crocus, Homepage. Retrieved from http://www.crocus-technology.com, 2016.

J. Das, M. Syed, S. Alam, and . Bhanja, STT-based non-volatile logic-in-memory framework, Field-Coupled Nanocomputing, pp.173-193, 2014.

C. Dirik, Performance analysis of NAND flash memory solid-state disks, 2009.

B. N. Engel, J. Åkerman, B. Butcher, R. W. Dave, M. Deherrera et al., A 4-Mb toggle MRAM based on a novel bit and switching method, IEEE Transactions on Magnetics, vol.41, issue.1, pp.1-132, 2005.
DOI : 10.1109/TMAG.2004.840847
URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.466.411

P. Gambardella and I. Miron, Current-induced spin-orbit torques, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, vol.80, issue.4, pp.1948-3175, 2011.
DOI : 10.1103/PhysRevLett.98.046601

Y. Guillemenet, L. Torres, and G. Sassatelli, Non-volatile run-time field-programmable gate arrays structures using thermally assisted switching magnetic random access memories, IET Computers & Digital Techniques, vol.4, issue.3, pp.3-211, 2010.
DOI : 10.1049/iet-cdt.2009.0019

R. Matthew, J. S. Guthaus, D. Ringenberg, T. M. Ernst, T. Austin et al., MiBench: A free, commercially representative embedded benchmark suite, IEEE International Workshop on Workload Characterization (WWC-4, pp.3-14, 2001.

C. Holland, First MRAM-based FPGA taped-out. Retrieved from http, p.4200035, 2010.

K. Ikegami, H. Noguchi, C. Kamata, M. Amano, K. Abe et al., Kawasumi, and others. 2014. A 4ns, 0.9 V write voltage embedded perpendicular STT-MRAM fabricated by MTJ-Last process, Proceedings of Technical Program-2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA, pp.1-2

K. Jabeur, G. D. Pendina, F. Bernard-granger, and G. Prenat, Spin Orbit Torque Non-Volatile Flip-Flop for High Speed and Low Energy Applications, IEEE Electron Device Letters, vol.35, issue.3, pp.3-408, 2014.
DOI : 10.1109/LED.2013.2297397

G. Jan, L. Thomas, S. Le, Y. Lee, H. Liu et al., Dongna Shen, and others. 2014. Demonstration of fully functional 8Mb perpendicular STT-MRAM chips with sub-5ns writing for non-volatile embedded memories, Digest of Technical Papers, 2014 Symposium on VLSI Technology (VLSI-Technology, pp.1-2

B. Jovanovic, R. M. Brum, and L. Torres, Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions, IEEE Transactions on Magnetics, vol.51, issue.2, pp.1-11, 2015.
DOI : 10.1109/TMAG.2014.2347009
URL : https://hal.archives-ouvertes.fr/lirmm-01284619

O. Jovanovi´cjovanovi´c, E. Thomas, J. M. Vianello, B. Portal, L. Nikoli´cnikoli´c et al., OxRAM-based non volatile flip-flop in 28nm FDSOI, 2014.

S. Karnouskos, P. J. Marrón, G. Fortino, L. Mottola, and J. Dios, Applications and Markets for Cooperating Objects, 2014.
DOI : 10.1007/978-3-642-45401-1

S. Khanna, S. Bartling, M. Clinton, S. Summerfelt, J. Rodriguez et al., Zero leakage microcontroller with 384ns wakeup time using FRAM mini-array architecture, 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), pp.21-24, 2013.
DOI : 10.1109/ASSCC.2013.6690972

S. Khanna, S. C. Bartling, M. Clinton, S. Summerfelt, J. A. Rodriguez et al., An FRAM-based nonvolatile logic MCU SoC exhibiting 100% digital state retention at 0 V achieving zero leakage with 400-ns wakeup time for ULP applications, IEEE J. Solid-State Circ, vol.49, pp.1-95, 2014.
DOI : 10.1109/jssc.2013.2284367

A. V. Khvalkovskiy, D. Apalkov, S. Watts, R. Chepulskii, R. S. Beach et al., Visscher, and others. 2013. Basic principles of STT-MRAM cell operation in memory arrays, J. Phys. D: Appl. Phys, vol.46, pp.7-74001, 2013.

H. Koike, S. Miura, H. Honjo, T. Watanabe, H. Sato et al., Yasuo Honjo, Naguchi, and others. 2016. Demonstration of yield improvement for on-via MTJ using a 2-Mbit 1T-1MTJ STT-MRAM test chip, 2016 IEEE 8th International Memory Workshop (IMW). IEEE, pp.1-4

H. Koike, T. Ohsawa, S. Ikeda, T. Hanyu, H. Ohno et al., Ayuka Morioka, and others. 2013. A power-gated MPU with 3-microsecond entry/exit delay using MTJ-based nonvolatile flip-flop, 2013 IEEE Asian Solid- State Circuits Conference, pp.317-320

K. Lewotsky, Tech trends: Details on everspins ST-MRAM. Retrieved from http, 2013.

K. Ma, Y. Zheng, S. Li, K. Swaminathan, X. Li et al., Architecture exploration for ambient energy harvesting nonvolatile processors, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA), pp.526-537, 2015.
DOI : 10.1109/HPCA.2015.7056060

J. Singh-meena, S. M. Sze, U. Chand, and T. Tseng, Overview of emerging nonvolatile memory technologies, Nanoscale Res. Lett, vol.9, issue.1, pp.1-33, 2014.

R. Micheloni, L. Crippa, and A. Marelli, Inside NAND Flash Memories, 2010.
DOI : 10.1007/978-90-481-9431-5

J. Subbaiah-moodera, L. R. Kinder, T. M. Wong, and R. Meservey, Large magnetoresistance at room temperature in ferromagnetic thin film tunnel junctions, Phys. Rev. Lett, vol.74, pp.16-3273, 1995.

T. Na, K. Ryu, J. Kim, S. Kang, and S. Jung, A comparative study of STT-MTJ based non-volatile flip-flops, 2013 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp.109-112, 2013.

H. Noguchi, K. Ikegami, K. Kushida, K. Abe, S. Itai et al., Hiroyuki Hara, and others. 2015. 7.5 a 3.3 ns-accesstime 71.2?W/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture, 2015 IEEE International Solid-State Circuits Conference-(ISSCC, pp.1-3

H. Noguchi, K. Kushida, K. Ikegami, K. Abe, E. Kitagawa et al., A 250-MHz 256b-I/O 1-Mb STT-MRAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors, 2013 Symposium on VLSI Technology (VLSIT, pp.108-109, 2013.

J. Janusz, R. P. Nowak, J. Z. Robertazzi, G. Sun, J. Hu et al., OSullivan, and others. 2016. Dependence of voltage and size on write error rates in spin-transfer torque magnetic random-access memory, IEEE Magnet. Lett, vol.7, 2016.

D. Pala, G. Causapruno, M. Vacca, F. Riente, G. Turvani et al., Logicin-memory architecture made real, 2015 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, pp.1542-1545, 2015.
DOI : 10.1109/iscas.2015.7168940

S. Paul, S. Mukhopadhyay, and S. Bhunia, A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA, IEEE Transactions on Nanotechnology, vol.10, issue.3, pp.3-385, 2011.
DOI : 10.1109/TNANO.2010.2041555

I. L. Prejbeanu, S. Bandiera, J. Alvarez-hérault, R. C. Sousa, B. Dieny et al., Thermally assisted MRAMs: ultimate scalability and logic functionalities, Journal of Physics D: Applied Physics, vol.46, issue.7, pp.7-074002, 2013.
DOI : 10.1088/0022-3727/46/7/074002

I. L. Prejbeanu, M. Kerekes, R. C. Sousa, H. Sibuet, O. Redon et al., Thermally assisted MRAM, Journal of Physics: Condensed Matter, vol.19, issue.16, pp.16-165218, 2007.
DOI : 10.1088/0953-8984/19/16/165218

N. Sakimura, Y. Tsuji, R. Nebashi, H. Honjo, A. Morioka et al., Shun Miura, Naoki Kasai, and others. 2014. 10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications, 2014 IEEE International Solid- State Circuits Conference Digest of Technical Papers (ISSCC, pp.184-185

C. Santifort, Amber ARM-compatible core, 2010.

O. Turkyilmaz, S. Onkaraiah, M. Reyboz, and F. Clermidy, Costin Anghel, Jean-Michel Portal, Marc Bocquet, and others. 2014. RRAM-based FPGA for normally off, instantly on applications

I. Wali, A. Virazel, A. Bosio, P. Girard, S. Pravossoudovitch et al., A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores, Journal of Electronic Testing, vol.59, issue.6, pp.1-15, 2016.
DOI : 10.1007/s10836-016-5578-0
URL : https://hal.archives-ouvertes.fr/lirmm-01354746

J. Wang, Y. Liu, H. Yang, and H. Wang, A compare-and-write ferroelectric nonvolatile flip-flop for energy-harvesting applications, The 2010 International Conference on Green Circuits and Systems, pp.646-650, 2010.
DOI : 10.1109/ICGCS.2010.5542984

R. P. Weicker, Dhrystone: a synthetic systems programming benchmark, Communications of the ACM, vol.27, issue.10, pp.1013-1030, 1984.
DOI : 10.1145/358274.358283

M. Xie, M. Zhao, C. Pan, J. Hu, Y. Liu et al., Fixing the broken time machine, Proceedings of the 52nd Annual Design Automation Conference on, DAC '15, 2015.
DOI : 10.1145/2744769.2744842

J. Yu, M. J. Garzarángarzar´garzarán, and M. Snir, Efficient software checking for fault tolerance, 2008 IEEE International Symposium on Parallel and Distributed Processing, pp.1-5, 2008.
DOI : 10.1109/IPDPS.2008.4536435

Y. Zhang, E. Y. Deng, J. O. Klein, D. Querlioz, D. Ravelosona et al., Michael Bocquet, and others. 2013. Synchronous full-adder based on complementary resistive switching memory cells, 2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS, pp.1-4

W. Zhao, M. Moreau, E. Deng, Y. Zhang, J. Portal et al., Synchronous Non-Volatile Logic Gate Design Based on Resistive Switching Memories, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, issue.2, pp.443-454, 2014.
DOI : 10.1109/TCSI.2013.2278332