F. Shearer, Power Management in Mobile Devices, Newnes, 2011.

E. Kitagawa, STT-MRAM cuts power use by 80%

S. Senni, L. Torres, G. Sassatelli, A. Bukto, and B. Mussard, Exploration of Magnetic RAM Based Memory Hierarchy for Multicore Architecture, 2014 IEEE Computer Society Annual Symposium on VLSI, pp.248-251, 2014.
DOI : 10.1109/ISVLSI.2014.29

URL : https://hal.archives-ouvertes.fr/lirmm-01253350

J. S. Moodera, L. R. Kinder, T. M. Wong, and R. Meservey, Large Magnetoresistance at Room Temperature in Ferromagnetic Thin Film Tunnel Junctions, Physical Review Letters, vol.74, issue.16, p.3273, 1995.
DOI : 10.1103/PhysRevLett.74.3273

B. Engel, A 4-Mb toggle MRAM based on a novel bit and switching method, IEEE Transactions on Magnetics, vol.41, issue.1, pp.132-136, 2005.
DOI : 10.1109/TMAG.2004.840847

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

I. Prejbeanu, Thermally assisted MRAM, Journal of Physics: Condensed Matter, vol.19, issue.16, p.165218, 2007.
DOI : 10.1088/0953-8984/19/16/165218

A. Khvalkovskiy, Basic principles of STT-MRAM cell operation in memory arrays, Journal of Physics D: Applied Physics, vol.46, issue.7, pp.74001-74020, 2013.
DOI : 10.1088/0022-3727/46/7/074001

P. Gambardella and I. M. Miron, Current-induced spin-orbit torques, Philosophical Transactions of the Royal Society A: Mathematical, Physical and Engineering Sciences, vol.80, issue.4, pp.3175-3197, 1948.
DOI : 10.1103/PhysRevLett.98.046601

K. Lewotsky and T. W. Andre, Tech trends: Details on Everspin's ST-MRAM Available: http://www.eetimes.com/document .asp? A 4-mb 1t1mtj toggle MRAM with balanced three input sensing scheme and locally mirrored unidirectional write drivers, IEEE J. Solid-State Circuits, vol.40, issue.1, pp.301-309, 2005.

I. Prejbeanu, Thermally assisted MRAMs: ultimate scalability and logic functionalities, Journal of Physics D: Applied Physics, vol.46, issue.7, p.74002, 2013.
DOI : 10.1088/0022-3727/46/7/074002

B. Cambou, Match in place. A novel way to perform secure and fast user's authentication [Online]. Available: www.crocus-technology

R. Bishnoi, M. Ebrahimi, F. Oboril, and M. B. Tahoori, Architectural aspects in design and analysis of SOT-based memories, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC), pp.700-707, 2014.
DOI : 10.1109/ASPDAC.2014.6742972

]. S. Lee, K. Kang, and C. Kyung, Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, issue.3, pp.520-533, 2015.
DOI : 10.1109/TVLSI.2014.2311798

J. Wang, X. Dong, and Y. Xie, OAP: An Obstruction-Aware Cache Management Policy for STT-RAM Last-Level Caches, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp.847-852, 2013.
DOI : 10.7873/DATE.2013.179

N. N. Mojumder, S. K. Gupta, S. H. Choday, D. E. Nikonov, and K. Roy, A Three-Terminal Dual-Pillar STT-MRAM for High-Performance Robust Memory Applications, IEEE Transactions on Electron Devices, vol.58, issue.5, pp.1508-1516, 2011.
DOI : 10.1109/TED.2011.2116024

S. Kang and K. Lee, Emerging materials and devices in spintronic integrated circuits for energy-smart mobile computing and connectivity, Acta Materialia, vol.61, issue.3, pp.952-973, 2013.
DOI : 10.1016/j.actamat.2012.10.036

X. Fong and K. Roy, Low-power robust complementary polarizer STT-MRAM (CPSTT) for on-chip caches, 2013 5th IEEE International Memory Workshop, pp.88-91, 2013.
DOI : 10.1109/IMW.2013.6582105

X. Fong and K. Roy, Complimentary Polarizers STT-MRAM (CPSTT) for On-Chip Caches, IEEE Electron Device Letters, vol.34, issue.2, pp.232-234, 2013.
DOI : 10.1109/LED.2012.2234079

H. Naeimi, C. Augustine, A. Raychowdhury, S. Lu, and J. Tschanz, STT-MRAM scaling and retention failure, Intel Technol. J, vol.17, issue.1, pp.54-75, 2013.

P. Khalili and K. Wang, Voltage-controlled MRAM: Status, challenges and prospects

J. G. Alzate, Voltage-induced switching of nanoscale magnetic tunnel junctions, 2012 International Electron Devices Meeting, pp.29-35, 2012.
DOI : 10.1109/IEDM.2012.6479130

S. Kanai, M. Yamanouchi, S. Ikeda, Y. Nakatani, F. Matsukura et al., Electric field-induced magnetization reversal in a perpendicular-anisotropy CoFeB-MgO magnetic tunnel junction, Applied Physics Letters, vol.101, issue.12, p.122403, 2012.
DOI : 10.1063/1.4753816

Y. Shiota, Induction of coherent magnetization switching in a few atomic layers of FeCo using voltage pulses, Nature Materials, vol.96, issue.1, pp.39-43, 2012.
DOI : 10.1063/1.1851881

Y. Shiota, Pulse voltage-induced dynamic magnetization switching in magnetic tunneling junctions with high resistance-area product, Applied Physics Letters, vol.101, issue.10, p.102406, 2012.
DOI : 10.1063/1.4751035

P. K. Amiri, P. Upadhyaya, J. Alzate, and K. Wang, Electric-field-induced thermally assisted switching of monodomain magnetic bits, Journal of Applied Physics, vol.113, issue.1, p.13912, 2013.
DOI : 10.1063/1.4773342

W. Wang, M. Li, S. Hageman, and C. Chien, Electric-field-assisted switching in magnetic tunnel??junctions, Nature Materials, vol.96, issue.1, pp.64-68, 2012.
DOI : 10.1063/1.3536482

K. Wang, J. Alzate, and P. K. Amiri, Low-power non-volatile spintronic memory: STT-RAM and beyond, Journal of Physics D: Applied Physics, vol.46, issue.7, p.74003, 2013.
DOI : 10.1088/0022-3727/46/7/074003

H. Noguchi, A 250-mHz 256b-i/o 1-mb STT-RAM with advanced perpendicular MTJ based dual cell for nonvolatile magnetic caches to reduce active power of processors, Proc. Symp, pp.108-109, 2013.

K. Ikegami, A 4 ns, 0.9 v write voltage embedded perpendicular STT-RAM fabricated by MTJ-Last process, Proc. Tech. Program- 2014 Int, pp.1-2, 2014.

H. Noguchi, 7.5 a 3.3 ns-access-time 1 mb embedded STT-RAM using physically eliminated read-disturb scheme and normally-off memory architecture, Proc. IEEE 2015 Int. Solid- State Circuits Conf, pp.1-3, 2015.

R. Dorrance, Diode-MTJ Crossbar Memory Cell Using Voltage-Induced Unipolar Switching for High-Density MRAM, IEEE Electron Device Letters, vol.34, issue.6, pp.753-755, 2013.
DOI : 10.1109/LED.2013.2255096

F. Oboril, R. Bishnoi, M. Ebrahimi, and M. B. Tahoori, Evaluation of Hybrid Memory Technologies Using SOT-MRAM for On-Chip Cache Hierarchy, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.34, issue.3, pp.367-380, 2015.
DOI : 10.1109/TCAD.2015.2391254

K. Jabeur, L. Buda-prejbeanu, G. Prenat, and G. Pendina, Study of two writing schemes for a magnetic tunnel junction based on spin orbit torque, Int. J. Electron. Sci. Eng, vol.7, issue.8, pp.501-507, 2013.

I. M. Miron, Current-driven spin torque induced by the Rashba effect in a ferromagnetic metal layer, Nature Materials, vol.102, issue.3, pp.230-234, 2010.
DOI : 10.1038/nmat2613

URL : https://hal.archives-ouvertes.fr/hal-00459160

L. Liu, Spin-Torque Switching with the Giant Spin Hall Effect of Tantalum, Science, vol.336, issue.6081, pp.555-558, 2012.
DOI : 10.1126/science.1218197

N. Binkert, The gem5 simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011.
DOI : 10.1145/2024716.2024718

A. Butko, A trace-driven approach for fast and accurate simulation of manycore architectures, The 20th Asia and South Pacific Design Automation Conference, pp.707-712
DOI : 10.1109/ASPDAC.2015.7059093

URL : https://hal.archives-ouvertes.fr/lirmm-01255921

X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory, IEEE Trans. Comput.-Aided Design Integr. Circuits Syst, vol.31, issue.7, pp.994-1007, 2012.
DOI : 10.1007/978-1-4419-9551-3_2

M. P. Komalan, C. Tenllado, J. I. Pérez, F. T. Fernández, and F. Catthoor, System Level Exploration of a STT-MRAM based Level 1 Data-Cache, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.1311-1316, 2015.
DOI : 10.7873/DATE.2015.0551

S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Gupta, The SPLASH-2 programs, ACM SIGARCH Computer Architecture News, vol.23, issue.2, pp.24-36, 1995.
DOI : 10.1145/225830.223990

C. Bienia, S. Kumar, J. P. Singh, and K. Li, The PARSEC benchmark suite, Proceedings of the 17th international conference on Parallel architectures and compilation techniques, PACT '08, pp.72-81, 2008.
DOI : 10.1145/1454115.1454128

C. Bienia, S. Kumar, and K. Li, PARSEC vs. SPLASH-2: A quantitative comparison of two multithreaded benchmark suites on Chip-Multiprocessors, 2008 IEEE International Symposium on Workload Characterization, pp.47-56, 2008.
DOI : 10.1109/IISWC.2008.4636090

X. Dong, Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, Proceedings of the 45th annual conference on Design automation, DAC '08, pp.554-559, 2008.
DOI : 10.1145/1391469.1391610

G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, A novel architecture of the 3D stacked MRAM L2 cache for CMPs, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.239-249, 2009.
DOI : 10.1109/HPCA.2009.4798259

X. Wu, Hybrid cache architecture with disparate memory technologies, ACM SIGARCH Computer Architecture News, vol.37, issue.3, pp.34-45, 2009.
DOI : 10.1145/1555815.1555761

X. Wu, J. Li, L. Zhang, E. Speight, and Y. Xie, Power and performance of read-write aware hybrid caches with non-volatile memories, IEEE Design, pp.737-742, 2009.

J. Li, C. J. Xue, and Y. Xu, STT-RAM based energy-efficiency hybrid cache for CMPs, 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, pp.31-36, 2011.
DOI : 10.1109/VLSISoC.2011.6081626

P. Zhou, B. Zhao, J. Yang, and Y. Zhang, Energy reduction for STT-RAM using early write termination, Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD '09, pp.264-268, 2009.
DOI : 10.1145/1687399.1687448

URL : http://citeseerx.ist.psu.edu/viewdoc/summary?doi=

K. Kwon, S. H. Choday, Y. Kim, and K. Roy, AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.4, pp.712-720, 2014.
DOI : 10.1109/TVLSI.2013.2256945

A. Jog, Cache revive, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.243-252
DOI : 10.1145/2228360.2228406

E. Arima, Fine-grain power-gating on STT-MRAM peripheral circuits with locality-aware access control, Memory Forum, 2014.

H. Noguchi, Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU, 2014 Symposium on VLSI Circuits Digest of Technical Papers, pp.1-2, 2014.
DOI : 10.1109/VLSIC.2014.6858403

F. A. Endo, D. Couroussé, and H. Charles, Micro-architectural simulation of embedded core heterogeneity with gem5 and McPAT, Proceedings of the 2015 Workshop on Rapid Simulation and Performance Evaluation Methods and Tools, RAPIDO '15, p.7, 2015.
DOI : 10.1145/2693433.2693440

P. Greenhalgh, Big. little processing with arm cortex-a15 & cortex- a7, pp.1-8, 2011.

W. Zhao and G. Prenat, Spintronics-Based Computing, 2015.
DOI : 10.1007/978-3-319-15180-9

D. Apalkov, Spin-transfer torque magnetic random access memory (STT-MRAM), ACM Journal on Emerging Technologies in Computing Systems, vol.9, issue.2, p.13, 2013.
DOI : 10.1145/2463585.2463589

S. P. Park, S. Gupta, N. Mojumder, A. Raghunathan, and K. Roy, Future cache design using STT MRAMs for improved energy efficiency, Proceedings of the 49th Annual Design Automation Conference on, DAC '12, pp.492-497
DOI : 10.1145/2228360.2228447

]. C. Augustine, Spin-Transfer Torque MRAMs for Low Power Memories: Perspective and Prospective, IEEE Sensors Journal, vol.12, issue.4, pp.756-766, 2012.
DOI : 10.1109/JSEN.2011.2124453

Y. Kim, S. K. Gupta, S. P. Park, G. Panagopoulos, and K. Roy, Writeoptimized reliable design of STT MRAM, Proc. 2012 ACM/IEEE Int. Symp. Low Power Electron. Design, pp.3-8, 2012.
DOI : 10.1145/2333660.2333664

S. Chatterjee, M. Rasquinha, S. Yalamanchili, and S. Mukhopadhyay, A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.5, pp.809-817, 2011.
DOI : 10.1109/TVLSI.2010.2041476

W. Cheng, Y. Ciou, and P. Shen, Architecture and data migration methodology for L1 cache design with hybrid SRAM and volatile STT-RAM configuration, Microprocessors and Microsystems, vol.42, 2015.
DOI : 10.1016/j.micpro.2015.11.005

J. Choi and G. Park, Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture, The Computer Journal, vol.59, issue.5, p.103, 2015.
DOI : 10.1093/comjnl/bxv103