Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes
Abstract
This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.
Keywords
silicon-on-insulator
integrated circuit testing
elemental semiconductors
FDSOI
Si
advanced technology nodes
fully depleted silicon on insulator
guard banding
hold margins
process variations
setup analysis
size 28 nm
test circuit
Clocks
Test Chip
Setup Time
Process Variation
Delays
Generators
Ring oscillators
Silicon
Tuning
Flip-flop
Hold Time
Timing Margins