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 Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes Deepak Kumar Arora 1105063-0 Darayus Adil Patel 888d9749eb81d3a6f1e59ddfb22144e8 lirmm.fr 982385 1029315-982385 https://orcid.org/0000-0002-7619-1734 Nc Shahabuddin 1105064-0 Sanjay Kumar 8e6684d1c3f1408e9f4eb11e0c5e46f1 gmail.com 839131 200120-839131 Navin Kumar Dayani 1105065-0 Balwant Singh 1105066-0 Sylvie Naudet 364732-0 Arnaud Virazel 514b9bdb53dacba2fd794d9140b751ae lirmm.fr arnaud-virazel 18065 17611-18065 https://www.idref.fr/068454724 http://isni.org/isni/0000000139422532 https://orcid.org/0000-0001-7398-7107 Alberto Bosio d520d64169c259e699ff959bd1bfad6f ec-lyon.fr alberto-bosio 172965 17774-172965 https://orcid.org/0000-0001-6116-7339 https://www.idref.fr/174383592 Arnaud Virazel 514b9bdb53dacba2fd794d9140b751ae lirmm.fr 2017-01-12 15:47:44 2025-08-13 03:12:29 2017-01-12 22:49:20 2016-03-15 contributor Arnaud Virazel 514b9bdb53dacba2fd794d9140b751ae lirmm.fr CCSD lirmm-01433314 https://hal-lirmm.ccsd.cnrs.fr/lirmm-01433314 arora:lirmm-01433314 <i>ISQED 2016 - 17th International Symposium on Quality Electronic Design</i>, Mar 2016, Santa Clara, CA, United States. pp.295-300, <a target="_blank" href="https://dx.doi.org/10.1109/ISQED.2016.7479217">&#x27E8;10.1109/ISQED.2016.7479217&#x27E9;</a> ISQED 2016 - 17th International Symposium on Quality Electronic Design, Mar 2016, Santa Clara, CA, United States. pp.295-300, &#x27E8;10.1109/ISQED.2016.7479217&#x27E9; CNRS - Centre national de la recherche scientifique SysMic Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier Test and dEpendability of microelectronic integrated SysTems MIC Département Microélectronique Mathématiques, Informatique, Physique et Systèmes Université de Montpellier Université de Montpellier (2015-2021) Centrale Lyon - périmètre strict International No No Yes Yes Analysis of Setup & Hold Margins Inside Silicon for Advanced Technology Nodes Deepak Kumar Arora 1105063-0 Darayus Adil Patel 888d9749eb81d3a6f1e59ddfb22144e8 lirmm.fr 982385 1029315-982385 https://orcid.org/0000-0002-7619-1734 Nc Shahabuddin 1105064-0 Sanjay Kumar 8e6684d1c3f1408e9f4eb11e0c5e46f1 gmail.com 839131 200120-839131 Navin Kumar Dayani 1105065-0 Balwant Singh 1105066-0 Sylvie Naudet 364732-0 Arnaud Virazel 514b9bdb53dacba2fd794d9140b751ae lirmm.fr arnaud-virazel 18065 17611-18065 https://www.idref.fr/068454724 http://isni.org/isni/0000000139422532 https://orcid.org/0000-0001-7398-7107 Alberto Bosio d520d64169c259e699ff959bd1bfad6f ec-lyon.fr alberto-bosio 172965 17774-172965 https://orcid.org/0000-0001-6116-7339 https://www.idref.fr/174383592 2016 17th International Symposium on Quality Electronic Design (ISQED) ISQED 2016 - 17th International Symposium on Quality Electronic Design 2016-03-15 2016-03-16 Santa Clara, CA United States IEEE 295-300 2016 10.1109/ISQED.2016.7479217 https://www.isqed.org/English/Archives/2016/index.html English Ring oscillators Timing Margins Hold Time Flip-flop Tuning Silicon size 28 nm integrated circuit testing elemental semiconductors FDSOI Si advanced technology nodes fully depleted silicon on insulator guard banding hold margins process variations setup analysis silicon-on-insulator test circuit Clocks Test Chip Setup Time Process Variation Delays Generators Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics Conference papers Conference papers Conference papers

This paper presents a design and methodology for accurate characterization of setup and hold margins in silicon while taking into account effects of Process Variations (PV). The test circuit provides deeper insights into sources of extra timing margins available on silicon. This in turn, enables accurate guard banding by preventing optimism and reducing unnecessary pessimism in the timing margins provided during sign-off. Our design has been used for the development of the 28nm Fully Depleted Silicon On Insulator (FDSOI) node and associated relevant results and analysis have been provided.

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