System-level reliability evaluation through cache-aware software-based fault injection

Firas Kaddachi 1 Maha Kooli 1 Giorgio Di Natale 1 Alberto Bosio 1 Mojtaba Ebrahimi 2 Mehdi B. Tahoori 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 KIT - Karlsruhe Institute of Technology
Abstract : Developing new methods to evaluate the software reliability in an early design stage of the system can save the design costs and efforts, and will positively impact the product time-to-market. In this paper, we propose a novel fault injection technique to evaluate the reliability of a computing system running a software at early design stage where the hardware architecture is not completely defined yet. The proposed approach efficiently operates on the original source code of the software in order to inject transient faults in the data or the instructions. To be accurate and to achieve a better characterization of the system, we simulate faults occurring in the system memory units such as the data cache and the RAM by developing a system emulator. To validate our approach, we compare the simulation results to those obtained with an FPGA-based fault injector. The similarity of the results proves the accuracy of our approach to evaluate system reliability with a gain in the execution time and without requiring a fully defined hardware system.
Keywords : Random access memory Hardware Software Software reliability Computer architecture Reliability engineering
Document type :
Conference papers
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01444721
Contributor : Caroline Lebrun <>
Submitted on : Tuesday, January 24, 2017 - 11:49:05 AM
Last modification on : Wednesday, July 24, 2019 - 5:13:51 PM

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LIRMM | CNRS | SYSMIC | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER | TEST

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Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, et al.. System-level reliability evaluation through cache-aware software-based fault injection. DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2016, Kosice, Slovakia. ⟨10.1109/DDECS.2016.7482446⟩. ⟨lirmm-01444721⟩

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