Low Power Oriented CMOS Circuit Optimization Protocol

Abstract : Low power oriented circuit optimization consists in selecting the best alternative between gate sizing, buffer insertion and logic structure transformation, for satisfying a delay constraint at minimum area cost. In this paper we used a closed form model of delay in CMOS structures to define metrics for a deterministic selection of the optimization alternative. The target is delay constraint satisfaction with minimum area cost. We validate the design space exploration method, defining maximum and minimum delay bounds on logical paths. Then we adapt this method to a "constant sensitivity method" allowing to size a circuit at minimum area under a delay constraint. An optimisation protocol is finally defined to manage the trade-off performance constraint - circuit structure. These methods are implemented in an optimization tool (POPS) and validated by comparing on a 0.25µm process, the optimization efficiency obtained on various benchmarks (ISCAS?85) to that resulting from an industrial tool.
Type de document :
Communication dans un congrès
DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. Design, Automation and Test in Europe, pp.640-645, 2005
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01507287
Contributeur : Isabelle Gouat <>
Soumis le : mercredi 12 avril 2017 - 19:00:17
Dernière modification le : mardi 23 octobre 2018 - 14:48:03

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  • HAL Id : lirmm-01507287, version 1
  • ARXIV : 0710.4760

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Alexandre Verle, Xavier Michel, Nadine Azemard, Philippe Maurine, Daniel Auvergne. Low Power Oriented CMOS Circuit Optimization Protocol. DATE: Design, Automation and Test in Europe, Mar 2005, Munich, Germany. Design, Automation and Test in Europe, pp.640-645, 2005. 〈lirmm-01507287〉

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