L. A. Belady, A study of replacement algorithms for a virtual-storage computer, IBM Systems Journal, vol.5, issue.2, pp.78-101, 1966.
DOI : 10.1147/sj.52.0078

X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, NVSim: A Circuit-Level Performance, Energy, and Area Model for Emerging Non-volatile Memory, IEEE Trans. on Computer-Aided Design of Integ. Circ. and Sys, issue.7, pp.31-994, 2012.
DOI : 10.1007/978-1-4419-9551-3_2

J. L. Henning, SPEC CPU2006 benchmark descriptions, ACM SIGARCH Computer Architecture News, vol.34, issue.4, pp.1-17, 2006.
DOI : 10.1145/1186736.1186737

A. Jain and C. Lin, Back to the future, Computer Architecture (ISCA) 2016 ACM/IEEE 43rd Annual International Symposium on, pp.78-89, 2016.
DOI : 10.1145/2155620.2155672

A. V. Kommaraju, Designing Energy-Aware Optimization Techniques through Program Behavior Analysis, 2014.

Q. Li, L. Shi, J. Li, C. J. Xue, and Y. He, Code Motion for Migration Minimization in STT-RAM Based Hybrid Cache, 2012 IEEE Computer Society Annual Symposium on VLSI, pp.410-415, 2012.
DOI : 10.1109/ISVLSI.2012.84

S. Mittal, A survey of architectural techniques for improving cache power efficiency, Sustainable Computing: Informatics and Systems, vol.4, issue.1, pp.33-43, 2014.
DOI : 10.1016/j.suscom.2013.11.001

URL : https://hal.archives-ouvertes.fr/hal-01103026

N. Muralimanohar, R. Balasubramonian, and N. P. Jouppi, CACTI 6.0: A tool to model large caches. HP Laboratories pp, pp.22-31, 2009.

P. Y. Péneau, R. Bouziane, A. Gamatié, E. Rohou, F. Bruguier et al., Loop optimization in presence of STT-MRAM caches: A study of performance-energy tradeoffs, 2016 26th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.162-169, 2016.
DOI : 10.1109/PATMOS.2016.7833682

C. W. Smullen, V. Mohan, A. Nigam, S. Gurumurthi, and M. R. Stan, Relaxing nonvolatility for fast and energy-efficient stt-ram caches, High Performance Computer Architecture (HPCA), 2011 IEEE 17th International Symposium on, pp.50-61, 2011.
DOI : 10.1109/hpca.2011.5749716

URL : http://www.cs.virginia.edu/~vm9u/files/RelaxingNV.pdf

G. Sun, X. Dong, Y. Xie, J. Li, and Y. Chen, A novel architecture of the 3D stacked MRAM L2 cache for CMPs, 2009 IEEE 15th International Symposium on High Performance Computer Architecture, pp.239-249, 2009.
DOI : 10.1109/HPCA.2009.4798259

J. S. Vetter and S. Mittal, Opportunities for Nonvolatile Memory Systems in Extreme-Scale High-Performance Computing, Computing in Science & Engineering, vol.17, issue.2, pp.73-82, 2015.
DOI : 10.1109/MCSE.2015.4

X. Wu, J. Li, L. Zhang, E. Speight, R. Rajamony et al., Hybrid cache architecture with disparate memory technologies, ACM SIGARCH Computer Architecture News, vol.37, issue.3, pp.34-45, 2009.
DOI : 10.1145/1555815.1555761

URL : http://taco-hca.googlecode.com/svn/trunk/ISCA2009.pdf

P. Zhou, B. Zhao, J. Yang, and Y. Zhang, Energy reduction for STT-RAM using early write termination, Proceedings of the 2009 International Conference on Computer-Aided Design, ICCAD '09, pp.264-268, 2009.
DOI : 10.1145/1687399.1687448

URL : http://www3.cs.pitt.edu/~zhangyt/research/iccad09.pdf