B. Yang, K. Wu, and R. Karri, Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard, ITC, pp.339-344, 2004.

J. Daemen and V. Rijmen, The Design of Rijndael, 2002.
DOI : 10.1007/978-3-662-04722-4

B. Yang, K. Wu, and R. Karri, Secure scan, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.135-140, 2005.
DOI : 10.1145/1065579.1065617

J. Darolt, G. D. Natale, M. Flottes, and B. Rouzeyre, Scan Attacks and Countermeasures in Presence of Scan Response Compactors, 2011 Sixteenth IEEE European Test Symposium, pp.19-24, 2011.
DOI : 10.1109/ETS.2011.30

J. Darolt, G. D. Natale, M. Flottes, and B. Rouzeyre, Are advanced DfT structures sufficient for preventing scanattacks? In VTS, pp.246-251, 2012.

O. Sk-subidh-ali, S. M. Sinanoglu, R. Saeed, and . Karri, New scan-based attack using only the test mode, VLSI-SoC, pp.234-239, 2013.

M. Doulcier, M. Flottes, and B. Rouzeyre, AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), pp.314-321, 2008.
DOI : 10.1109/DELTA.2008.86
URL : https://hal.archives-ouvertes.fr/lirmm-00258769

G. Chiu and J. Li, A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, issue.1, pp.126-134, 2010.
DOI : 10.1109/TVLSI.2010.2089071

D. Hely, M. Flottes, F. Bancel, B. Rouzeyere, and N. Bernard, Scan design and secure chip, Proc. IEEE Int. On-Line Test. Symp, pp.219-224, 2004.
DOI : 10.1109/olt.2004.1319691
URL : https://hal.archives-ouvertes.fr/lirmm-00108909

H. Fujiwara and K. Fujiwara, Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers, IEICE Transactions on Information and Systems, vol.98, issue.10, pp.1852-1855, 2015.
DOI : 10.1587/transinf.2015EDL8100

D. Rolt, J. Di-natale, G. Flottes, M. Rouzeyre, and B. , Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison, Proc. IEEE Trans. on Very Large Scale Integration (VLSI) System, pp.947-951, 2013.
DOI : 10.1109/TVLSI.2013.2257903
URL : https://hal.archives-ouvertes.fr/lirmm-00841650

K. Rosenfeld and R. Karri, Attacks and Defenses for JTAG, IEEE Design & Test of Computers, vol.27, issue.1, pp.36-47, 2010.
DOI : 10.1109/MDT.2010.9

G. , D. Natale, M. Doulcier, M. L. Flottes, and B. Rouzeyre, Self-Test Techniques for Crypto-Devices, IEEE Transaction on VLSI Systems, issue.2, pp.1-518, 2008.
DOI : 10.1109/tvlsi.2008.2010045
URL : https://hal.archives-ouvertes.fr/lirmm-00365359

A. Schubert and W. Anheier, On random pattern testability of cryptographic VLSI cores, European Test Workshop 1999 (Cat. No.PR00390), pp.185-192, 2000.
DOI : 10.1109/ETW.1999.803820

A. Poschmann, A. Moradi, K. Khoo, C. Lim, H. Wang et al., Side-Channel Resistant Crypto for Less than 2,300 GE, Journal of Cryptology, vol.3, issue.3, pp.322-345, 2011.
DOI : 10.1109/DATE.2005.241