M. Owaida, Enhancing Design Space Exploration by Extending CPU/GPU Specifications onto FPGAs, ACM Transactions on Embedded Computing Systems, vol.14, issue.2, pp.1-3323, 2015.
DOI : 10.1109/ISCAS.2012.6272149

D. Carey, R. Lowdermilk, and M. Spinali, Testing software defined and cognitive radios using software defined synthetic instruments, IEEE Instrumentation & Measurement Magazine, vol.18, issue.2, pp.19-24, 2015.
DOI : 10.1109/MIM.2015.7066678

R. G. Gallager, Low-density parity-check codes, IEEE Transactions on Information Theory, vol.8, issue.1, pp.21-28, 1962.
DOI : 10.1109/TIT.1962.1057683

P. Hailes, L. Xu, R. G. Maunder, B. M. Hashimi, and L. Hanzo, A Survey of FPGA-Based LDPC Decoders, IEEE Communications Surveys & Tutorials, vol.18, issue.2, pp.1098-1122, 2016.
DOI : 10.1109/COMST.2015.2510381

J. Andrade, G. Falcao, and V. Silva, Flexible design of wide-pipeline-based WiMAX QC-LDPC decoder architectures on FPGAs using high-level synthesis, Electronics Letters, vol.50, issue.11, pp.839-840, 2014.
DOI : 10.1049/el.2013.3411

G. Falcao, Configurable M-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design, EURASIP Journal on Wireless Communications and Networking, vol.55, issue.3, p.98, 2012.
DOI : 10.1109/TCE.2009.5277954
URL : http://doi.org/10.1186/1687-1499-2012-98

C. Marchand, L. Conde-canencia, and E. Boutillon, Architecture and finite precision optimization for layered LDPC decoders, Proc. IEEE Int. Conf. Appl.-Specific Syst., Archit. Process, pp.350-355, 2010.
DOI : 10.1007/s11265-011-0604-z
URL : https://hal.archives-ouvertes.fr/hal-00663385

A. Balatsoukas-stimming and A. Dollas, FPGA-based design and implementation of a multi-GBPS LDPC decoder, 22nd International Conference on Field Programmable Logic and Applications (FPL), pp.262-269, 2012.
DOI : 10.1109/FPL.2012.6339191

D. C. Alves, E. D. Lima, and J. E. Bertuzzo, A pipelined semiparallel LDPC Decoder architecture for DVB-S2, Proc. 3rd Workshop Circuits Syst. Des. (WCAS), pp.1-4, 2013.

O. Boncalo, A. Amaricai, A. Hera, and V. Savin, Cost-efficient FPGA layered LDPC decoder with serial AP-LLR processing, 2014 24th International Conference on Field Programmable Logic and Applications (FPL), pp.1-6, 2014.
DOI : 10.1109/FPL.2014.6927474

A. J. Blanksby and C. J. Howland, A 690-mW 1-Gb/s 1024-b, rate-1/2 low-density parity-check code decoder, IEEE Journal of Solid-State Circuits, vol.37, issue.3, pp.404-412, 2002.
DOI : 10.1109/4.987093

A. M. Wyglinski, D. P. Orofino, M. N. Ettus, and T. W. Rondeau, Revolutionizing software defined radio: case studies in hardware, software, and education, IEEE Communications Magazine, vol.54, issue.1, pp.68-75, 2016.
DOI : 10.1109/MCOM.2016.7378428

R. A. Carrasco and M. Johnston, Non-Binary Error Control Coding for Wireless Communication and Data Storage, 2008.
DOI : 10.1002/9780470740415

J. Andrade, G. Falcao, V. Silva, J. P. Barreto, N. Goncalves et al., Near-LSPA performance at MSA complexity, 2013 IEEE International Conference on Communications (ICC), pp.3281-3285, 2013.
DOI : 10.1109/ICC.2013.6655051

J. Andrade, G. Falcao, V. Silva, and K. Kasai, Flexible non-binary LDPC decoding on FPGAs, 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), pp.1936-1940, 2014.
DOI : 10.1109/ICASSP.2014.6853936

J. O. Lacruz, Simplified Trellis Min???Max Decoder Architecture for Nonbinary Low-Density Parity-Check Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.23, issue.9, pp.1783-1792, 2015.
DOI : 10.1109/TVLSI.2014.2344113
URL : https://riunet.upv.es/bitstream/10251/65131/3/TMM_AV.pdf

G. Wang, Parallel nonbinary LDPC decoding on GPU, 2012 Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), pp.1277-1281, 2012.
DOI : 10.1109/ACSSC.2012.6489229
URL : http://www.ece.rice.edu/%7Eby2/papers/Asilomar12_GPU_NBLDPC_submitted.pdf

M. Owaida, Massively parallel programming models used as hardware description languages: The OpenCL case, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), pp.326-333, 2011.
DOI : 10.1109/ICCAD.2011.6105349

O. Pell and V. Averbukh, Maximum Performance Computing with Dataflow Engines, Computing in Science & Engineering, vol.14, issue.4, pp.98-103, 2012.
DOI : 10.1109/MCSE.2012.78

J. Andrade, Fast Design Space Exploration Using Vivado HLS: Non-binary LDPC Decoders, 2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines, p.97, 2015.
DOI : 10.1109/FCCM.2015.63

G. Falcao, V. Silva, L. Sousa, and J. Andrade, Portable LDPC Decoding on Multicores Using OpenCL [Applications Corner], IEEE Signal Processing Magazine, vol.29, issue.4, pp.81-109, 2012.
DOI : 10.1109/MSP.2012.2192212

C. Roth, A. Cevrero, C. Studer, Y. Leblebici, and A. Burg, Area, throughput, and energy-efficiency trade-offs in the VLSI implementation of LDPC decoders, 2011 IEEE International Symposium of Circuits and Systems (ISCAS), pp.1772-1775, 2011.
DOI : 10.1109/ISCAS.2011.5937927

J. Andrade, F. Pratas, G. Falcao, V. Silva, and L. Sousa, Combining flexibility with low power: Dataflow and wide-pipeline LDPC decoding engines in the Gbit/s era, 2014 IEEE 25th International Conference on Application-Specific Systems, Architectures and Processors, pp.264-269, 2014.
DOI : 10.1109/ASAP.2014.6868671

J. Andrade, From low-architectural expertise up to high-throughput non-binary LDPC decoders: Optimization guidelines using high-level synthesis, 2015 25th International Conference on Field Programmable Logic and Applications (FPL), pp.1-8, 2015.
DOI : 10.1109/FPL.2015.7293940

K. Kasai and K. Sakaniwa, Fourier domain decoding algorithm of nonbinary LDPC codes for parallel implementation, Proc. IEEE Int. Conf. Accoustics, Speech Signal Process, pp.3128-3131, 2011.

X. Zhang and F. Cai, Reduced-Complexity Decoder Architecture for Non-Binary LDPC Codes, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.19, issue.7, pp.1229-1238, 2011.
DOI : 10.1109/TVLSI.2010.2047956

F. García-herrero, M. J. Canet, and J. Valls, High-speed NB-LDPC decoder for wireless applications, 2013 International Symposium on Intelligent Signal Processing and Communication Systems, pp.215-220, 2013.
DOI : 10.1109/ISPACS.2013.6704549

J. O. Lacruz, F. García-herrero, M. J. Canet, J. Valls, and A. Pérez, A 630 Mbps non-binary LDPC decoder for FPGA, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1989-1992, 2015.
DOI : 10.1109/ISCAS.2015.7169065
URL : https://riunet.upv.es/bitstream/10251/70703/2/A%20630%20Mbps%20Non-Binary%20LDPC%20Decoder%20for%20FPGA_version%20editorial.pdf

W. Sulek, M. Kucharczyk, and G. Dziwoki, GF(q) LDPC decoder design for FPGA implementation, 2013 IEEE 10th Consumer Communications and Networking Conference (CCNC), pp.460-465, 2013.
DOI : 10.1109/CCNC.2013.6488484

F. Liu and H. Li, Decoder Design for Non-Binary LDPC Codes, 2011 7th International Conference on Wireless Communications, Networking and Mobile Computing, pp.1-4, 2011.
DOI : 10.1109/wicom.2011.6040195

T. Lehnigk-emden and N. Wehn, Complexity evaluation of non-binary Galois field LDPC code decoders, 2010 6th International Symposium on Turbo Codes & Iterative Information Processing, pp.53-57, 2010.
DOI : 10.1109/ISTC.2010.5613874

E. Boutillon, L. Conde-canencia, and A. A. , Design of a GF(64)-LDPC Decoder Based on the EMS Algorithm, IEEE Transactions on Circuits and Systems I: Regular Papers, vol.60, issue.10, pp.2644-2656, 2013.
DOI : 10.1109/TCSI.2013.2279186
URL : https://hal.archives-ouvertes.fr/hal-00777131

C. Spagnol, W. Marnane, and E. Popovici, FPGA implementations of LDPC over GF(2 m ) decoders, Proc. IEEE Int, pp.273-278, 2007.

R. Tessier, K. Pocek, and A. Dehon, Reconfigurable Computing Architectures, Proc. IEEE, pp.332-354, 2015.
DOI : 10.1109/JPROC.2014.2386883

A. Canis, LegUp, Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays, FPGA '11, pp.33-36, 2011.
DOI : 10.1145/1950413.1950423

J. Villarreal, Designing Modular Hardware Accelerators in C with ROCCC 2.0, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, pp.127-134, 2010.
DOI : 10.1109/FCCM.2010.28
URL : http://www1.cse.wustl.edu/~roger/565M.f12/ROCCC.pdf

A. Papakonstantinou, FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs, 2009 IEEE 7th Symposium on Application Specific Processors, pp.35-42, 2009.
DOI : 10.1109/SASP.2009.5226333

I. Mavroidis, FASTCUDA: Open Source FPGA Accelerator & Hardware-Software Codesign Toolset for CUDA Kernels, 2012 15th Euromicro Conference on Digital System Design, pp.343-348, 2012.
DOI : 10.1109/DSD.2012.58
URL : http://porto.polito.it/2507481/1/fastcuda_submitted.pdf

J. Andrade-received-the and M. Sc, D. degree in electrical and computer engineering from the University of Coimbra. From 2010 to 2016, he was a Researcher with the Instituto de Telecomunicações and an Affiliated Member of the HiPEAC Since 2016, he has been a Research and Development Engineer with Synopsys Porto His research interests include hardware verification , error resilient architectures, forward errorcorrection , and reconfigurable computing, degree in telecommunications and the Ph NITHIN GEORGE received the Ph.D. degree in computer science from the École Polytechnique Fédérale de Lausanne in 2016, and the M.Sc. degree in communication engineering from the Technische Universität München in 2009. He is currently a Software Engineer with Intel Technologies . His research interests include high-level synthesis, hardware design targeting FPGAs, and developing domain-specific tools

K. Karras-received-the and B. Sc, degree from the Technical Educational Institute of Pireaus, the M.Sc. degree in microelectronics from the University of Athens, and the Ph.D. degree from the Technische Universität München. He was a Research Engineer with Xilinx Research Labs, Ireland. He is currently with Think Silicon S.A., where he is responsible for hardware development. His research interests include high-performance data center platforms, high-level synthesis, and networking for data centers

D. Novo, LIRMM, France, for one year. Since 2017, he has been a Tenured Full-Time CNRS Research Scientist with LIRMM. His research interests include hardware and software techniques for increasing computational efficiency in next-generation computers, he was a Post-Doctoral Researcher with the Processor Architecture Laboratory, EPFL, Switzerland, for five years, and with the Adaptive Computing Group FREDERICO PRATAS (S'07?M'13) received the Ph.D. degree in electrical and computer engineering from the Instituto Superior Técnico 2012. Until 2013, he was also a Researcher with INESC-ID, Lisbon. In 2013, he was a Researcher Scientist with Intel Labs involving in the design of future microarchitectures. Since 2014, he has been with the Imagination Technologies' MIPS Group, KL, U.K., where he currently collaborates as a Leading Hardware Design Engineer. His research interests include computer architectures and microarchitectures design and verification, highperformance computing, and reconfigurable computing, 2005.

P. Ienne, 10) received the Ph.D. degree in computer science from the École Polytechnique Fédérale de Lausanne. He is currently a Professor with the School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne, where he heads the Processor Architecture Laboratory. His research interests include computer and processor architecture , electronic design automation, computer arithmetic, FPGAs and reconfigurable computing, and multiprocessor systems-on-chip