B. Yang, K. Wu, and R. Karri, Scan Based Side Channel Attack on Dedicated Hardware Implementations of Data Encryption Standard, ITC, pp.339-344, 2004.

J. Darolt, G. D. Natale, M. Flottes, and B. Rouzeyre, Scan Attacks and Countermeasures in Presence of Scan Response Compactors, 2011 Sixteenth IEEE European Test Symposium, pp.19-24, 2011.
DOI : 10.1109/ETS.2011.30

D. Hely, M. Flottes, F. Bancel, B. Rouzeyere, and N. Bernard, Scan design and secure chip, Proc. IEEE Int. On-Line Test. Symp, pp.219-224, 2004.
DOI : 10.1109/olt.2004.1319691

URL : https://hal.archives-ouvertes.fr/lirmm-00108909

D. Rolt, J. Di-natale, G. Flottes, M. Rouzeyre, and B. , Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison, Proc. IEEE Trans. on Very Large Scale Integration (VLSI) System, pp.947-951, 2013.
DOI : 10.1109/TVLSI.2013.2257903

URL : https://hal.archives-ouvertes.fr/lirmm-00841650

M. Doulcier, M. Flottes, and B. Rouzeyre, AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), pp.314-321, 2008.
DOI : 10.1109/DELTA.2008.86

URL : https://hal.archives-ouvertes.fr/lirmm-00258769

G. Chiu and J. Li, A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.20, issue.1, pp.126-134, 2010.
DOI : 10.1109/TVLSI.2010.2089071

K. Rosenfeld and R. Karri, Attacks and Defenses for JTAG, IEEE Design & Test of Computers, vol.27, issue.1, pp.36-47, 2010.
DOI : 10.1109/MDT.2010.9

M. Mathieu-da-silva, G. D. Flottes, B. Natale, M. Rouzeyre, P. Restifo et al., Scan Chain Encryption for the Test, Diagnosis and Debug of Secure Circuits, 22 nd IEEE European Test Symposium (ETS'17)

, FIGURE Fig. 1. Scan chain encryption implementation