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Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level

Charles Effiong 1 Abdoulaye Gamatié 1 Gilles Sassatelli 1
1 ADAC - ADAptive Computing
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : This paper presents an RTL design and evaluation framework allowing the designer to easily build and analyze 3D NoC models with customizable defect threshold on Through-Silicon-Via (TSV) vertical links. The framework provides enough flexibility for addressing 3D NoC design issues, such as process variability, which can introduce open-resistive TSVs in the design, caused by impurities and/or defect during manufacturing process. Such TSVs lead to slower data transfers compared to non defective TSVs. To illustrate the usage of the framework usage, we evaluate typical application mappings in a 3D NoC multicore system to mitigate the performance penalty related to process variability.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-01870671
Contributor : Abdoulaye Gamatié <>
Submitted on : Saturday, September 8, 2018 - 6:40:06 PM
Last modification on : Tuesday, May 12, 2020 - 11:06:01 AM
Document(s) archivé(s) le : Sunday, December 9, 2018 - 12:22:58 PM

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Charles Effiong, Abdoulaye Gamatié, Gilles Sassatelli. Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level. [Research Report] LIRMM (UM, CNRS). 2018. ⟨lirmm-01870671⟩

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