Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Reports (Research Report) Year : 2018

Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level

Charles Emmanuel Effiong
Abdoulaye Gamatié
Gilles Sassatelli

Abstract

This paper presents an RTL design and evaluation framework allowing the designer to easily build and analyze 3D NoC models with customizable defect threshold on Through-Silicon-Via (TSV) vertical links. The framework provides enough flexibility for addressing 3D NoC design issues, such as process variability, which can introduce open-resistive TSVs in the design, caused by impurities and/or defect during manufacturing process. Such TSVs lead to slower data transfers compared to non defective TSVs. To illustrate the usage of the framework usage, we evaluate typical application mappings in a 3D NoC multicore system to mitigate the performance penalty related to process variability.
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Dates and versions

lirmm-01870671 , version 1 (08-09-2018)

Identifiers

  • HAL Id : lirmm-01870671 , version 1

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Charles Emmanuel Effiong, Abdoulaye Gamatié, Gilles Sassatelli. Design Exploration Framework for 3D-NoC Multicore Systems under Process Variability at RTL level. [Research Report] LIRMM (UM, CNRS). 2018. ⟨lirmm-01870671⟩
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