M. J. Flynn and P. Hung, Microprocessor design issues: thoughts on the road ahead, IEEE Micro, vol.25, issue.3, pp.16-31, 2005.
DOI : 10.1109/mm.2005.56

R. Kumar, D. M. Tullsen, P. Ranganathan, N. P. Jouppi, and K. I. Farkas, Single-ISA heterogeneous multi-core architectures for multithreaded workload performance, Proceedings of the International Symposium on Computer Architecture (ISCA), pp.64-75, 2004.
DOI : 10.1145/1028176.1006707
URL : http://www-cse.ucsd.edu/users/tullsen/micro03.pdf

R. Kumar, D. M. Tullsen, and N. P. Jouppi, Core architecture optimization for heterogeneous chip multiprocessors, Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.23-32, 2006.
DOI : 10.1145/1152154.1152162
URL : http://www-cse.ucsd.edu/users/tullsen/pact06.pdf

J. C. Mogul, J. Mudigonda, N. Binkert, P. Ranganathan, and V. Talwar, Using asymmetric single-ISA CMPs to save energy on operating systems, IEEE Micro, vol.28, issue.3, 2008.
DOI : 10.1109/mm.2008.47

K. Van-craeynest and L. Eeckhout, Understanding fundamental design choices in single-ISA heterogeneous multicore architectures, ACM Transactions on Architecture and Code Optimization (TACO), vol.9, issue.4, p.32, 2013.

S. L. Xi, H. Jacobson, P. Bose, G. Wei, and D. Brooks, Quantifying sources of error in McPAT and potential impacts on architectural studies, Proceedings of the International Symposium on High Performance Computer Architecture (HPCA), pp.577-589, 2015.

. Mediatek, MediaTek helio X20, 2018.

. Samsung, Exynos 7 Octa (7420), 2018.

&. B. Arm and . Little, , 2018.

. Mediatek, CorePilot 3.0. Max.Mid.Min (Tri-Cluster) technology to maximize power efficiency with extreme computing performance, Tech. Rep, 2015.

S. Che, M. Boyer, J. Meng, D. Tarjan, J. W. Sheaffer et al., Rodinia: A benchmark suite for heterogeneous computing, Proceedings of the IEEE International Symposium on Workload Characterization, pp.44-54, 2009.