M. Imani, S. Gupta, and T. Rosing, Ultra-efficient processing inmemory for data intensive applications, Proceedings of the 54th Annual Design Automation Conference, vol.6, pp.1-6, 2017.

J. Zhou, X. Yang, and J. Wu, A memristor-based architecture combining memory and image processing, Sci. China Inform. Sci, vol.57, issue.5, pp.1-12, 2014.

N. S. Kim, T. Austin, and D. Blaauw, Leakage current: Moore's law meets static power, Computer, vol.36, issue.12, pp.68-75, 2003.

S. W. Keckler, W. J. Dally, and B. Khailany, GPUs and the future of parallel computing, IEEE Micro, vol.31, issue.5, pp.7-17, 2011.

S. Li, C. Xu, and Q. Zou, Pinatubo: A processing-in-memory architecture for bulk bitwise operations in emerging non-volatile memories, 2016 53nd ACM/EDAC/IEEE Design Automation Conference, pp.1-6, 2016.

L. Koskinen, J. Tissari, and J. Teittinen, A performance case-study on memristive computing-in-memory versus Von Neumann architecture, 2016 Data Compression Conference, pp.613-613, 2016.

J. Ahn, S. Hong, and S. Yoo, A scalable processing-in-memory accelerator for parallel graph processing, 2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture, pp.105-117, 2015.

K. Chen, S. Li, and N. Muralimanohar, CACTI-3DD: Architecturelevel modeling for 3D die-stacked DRAM main memory, p.2012

. Design, Automation Test in Europe Conference Exhibition, pp.33-38, 2012.

X. Dong, X. Wu, and G. Sun, Circuit and microarchitecture evaluation of 3D stacking magnetic RAM (MRAM) as a universal memory replacement, 45th ACM/IEEE Design Automation Conference, pp.554-559, 2008.

W. Zhao and G. Prenat, Spintronics-Based Computing, 2015.
URL : https://hal.archives-ouvertes.fr/hal-01976638

C. J. Xue, G. Sun, and Y. Zhang, Emerging non-volatile memories: opportunities and challenges, IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp.325-334, 2011.

F. Parveen, S. Angizi, and Z. He, Low power in-memory computing based on dual-mode SOT-MRAM, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, pp.1-6, 2017.

W. Kang, Z. Wang, and Y. Zhang, Spintronic logic design methodology based on spin hall effect-driven magnetic tunnel junctions, J. Phys. D: Appl. Phys, vol.49, issue.6, p.65008, 2016.

H. Zhang, W. Kang, and L. Wang, Stateful reconfigurable logic via a single-voltage-gated spin hall-effect driven magnetic tunnel junction in a spintronic memory, IEEE Trans. Electron Devices, vol.64, issue.10, pp.4295-4301, 2017.

W. Kang, Y. Zhang, and Z. Wang, Spintronics: Emerging ultra-lowpower circuits and systems beyond MOS technology, ACM J. Emerg. Technol. Comput. Syst, vol.12, issue.2, pp.1-16, 2015.

S. A. Wolf, D. D. Awschalom, and R. A. Buhrman, Spintronics: A spin-based electronics vision for the future, Science, vol.294, issue.5546, pp.1488-1495, 2001.

H. S. Wong and S. Salahuddin, Memory leads the way to better computing, Nat. Nanotechnol, vol.10, issue.3, pp.191-194, 2015.

W. Kang, L. Zhang, and J. Klein, Reconfigurable codesign of STT-MRAM under process variations in deeply scaled technology, IEEE Trans. Electron Devices, vol.62, issue.6, pp.1769-1777, 2015.

D. Patterson, T. Anderson, and N. Cardwell, A case for intelligent ram, IEEE Micro, vol.17, issue.2, pp.34-44, 1997.

M. Imani, Y. Kim, and T. Rosing, MPIM: Multi-purpose in-memory processing using configurable resistive memory, 2017 22nd Asia and South Pacific Design Automation Conference, pp.757-763, 2017.

D. Fan, S. Angizi, and Z. He, In-memory computing with spintronic devices, 2017 IEEE Computer Society Annual Symposium on VLSI, pp.683-688, 2017.

J. Yu, R. Nane, and A. Haron, Skeleton-based design and simulation flow for computation-in-memory architectures, 2016 IEEE/ACM International Symposium on Nanoscale Architectures, pp.165-170, 2016.

A. Haron, J. Yu, and R. Nane, Parallel matrix multiplication on memristor-based computation-in-memory architecture, 2016 International Conference on High Performance Computing Simulation, pp.759-766, 2016.

S. Hamdioui, M. Taouil, and H. A. Nguyen, CIM100x: Computation in-memory architecture based on resistive devices, 2016 15th International Workshop on Cellular Nanoscale Networks and their Applications, pp.1-2, 2016.

P. Chi, S. Li, and C. Xu, PRIME: A novel processing-in-memory architecture for neural network computation in ReRAM-based main memory, 2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture, vol.44, pp.27-39, 2016.

W. Kang, H. Wang, and Z. Wang, In-memory processing paradigm for bitwise logic operations in STT-MRAM, IEEE Trans. Magn, vol.53, issue.11, pp.1-4, 2017.

S. Hamdioui, L. Xie, and H. A. Nguyen, Memristor based computation-in-memory architecture for data-intensive applications, Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, pp.1718-1725, 2015.

S. Hamdioui, M. Taouil, and H. A. Nguyen, Memristor: the enabler of computation-in-memory architecture for big-data, 2015 International Conference on Memristive Systems, pp.1-3, 2015.

S. Hamdioui, Computation in memory for data-intensive applications: Beyond CMOS and beyond Von-Neumann, Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, pp.1-1, 2015.

J. J. Yang, D. B. Strukov, and D. R. Stewart, Memristive devices for computing, Nat. Nanotechnol, vol.8, issue.1, pp.13-24, 2013.

L. Zhang, W. Kang, and Y. Zhang, Channel modeling and reliability enhancement design techniques for STT-MRAM, 2015 IEEE Computer Society Annual Symposium on VLSI, pp.461-466, 2015.

H. Cai, Y. Wang, and L. A. Naviner, Robust ultra-low power non-volatile logic-in-memory circuits in FD-SOI technology, IEEE Trans. Circuits Syst. I, vol.64, issue.4, pp.847-857, 2017.
URL : https://hal.archives-ouvertes.fr/hal-02287638

W. Zhao, C. Chappert, and V. Javerliac, High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits, IEEE Trans. Magn, vol.45, issue.10, pp.3784-3787, 2009.

W. Zhao and Y. Cao, Predictive technology model for nano-CMOS design exploration, ACM J. Emerg. Technol. Comput. Syst, vol.3, issue.1, 2007.

Y. Wang, Y. Zhang, and E. Deng, Compact model of magnetic tunnel junction with stochastic spin transfer torque switching for reliability analyses, Microelectron. Reliab, vol.54, issue.9, pp.1774-1778, 2014.
URL : https://hal.archives-ouvertes.fr/hal-01216414

L. Zhang, A. Todri-sanial, and W. Kang, Quantitative evaluation of reliability and performance for STT-MRAM, 2016 IEEE International Symposium on Circuits and Systems, pp.1150-1153, 2016.
URL : https://hal.archives-ouvertes.fr/lirmm-01446275

L. Zhang, Y. Cheng, and W. Kang, Addressing the thermal issues of stt-mram from compact modeling to design techniques, IEEE Trans. Nanotechnol, vol.17, issue.2, pp.345-352, 2018.
URL : https://hal.archives-ouvertes.fr/lirmm-01880065

M. Wang, W. Cai, and K. Cao, Current-induced magnetization switching in atom-thick tungsten engineered perpendicular magnetic tunnel junctions with large tunnel magnetoresistance, Nat. Commun, vol.9, issue.1, p.671, 2018.