Electromigration and voltage drop aware power grid optimization for power gated ICs - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Accéder directement au contenu
Communication Dans Un Congrès Année : 2007

Electromigration and voltage drop aware power grid optimization for power gated ICs

Résumé

Power gating is an efficient technique for reducing leakage power by disconnecting idle blocks from power supply. Gated blocks cause changes in current densities on the grid. Even in DC conditions for some power gating configuration (PGC), current densities in some branches may increase to the extent of violating electromigration (EM) constraints. The existing DC methods optimize the grid under voltage drop (IR) and EM constraints for a single configuration of blocks. We analyze the effects of power gating and develop a grid sizing algorithm to satisfy all reliability constraints for multiple PGCs with only a small increase in area.
Fichier non déposé

Dates et versions

lirmm-01973890 , version 1 (08-01-2019)

Identifiants

Citer

Aida Todri-Sanial, Shih-Chieh Chang, Malgorzata Marek-Sadowska. Electromigration and voltage drop aware power grid optimization for power gated ICs. ISLPED: International Symposium on Low Power Electronics and Design, 2007, Portland, OR, United States. ⟨10.1145/1283780.1283866⟩. ⟨lirmm-01973890⟩

Collections

LIRMM
59 Consultations
0 Téléchargements

Altmetric

Partager

Gmail Facebook X LinkedIn More