Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2009

Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS

David Novo
R. Fasthuber
  • Function : Author
P. Raghavan
  • Function : Author
A. Bourdoux
  • Function : Author
Min Li
L. van Der Perre
  • Function : Author
F. Catthoor
  • Function : Author
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lirmm-02089304 , version 1 (03-04-2019)

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David Novo, R. Fasthuber, P. Raghavan, A. Bourdoux, Min Li, et al.. Power-aware evaluation flowfor digital decimation filter architectures for high-speed ADCS. IEEE Workshop on Signal Processing Systems (SiPS), Oct 2009, Tampere, Finland. pp.151-156, ⟨10.1109/SIPS.2009.5336241⟩. ⟨lirmm-02089304⟩

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