, big.LITTLE Technology: The Future of Mobile, 2013.

D. Pandiyan and C. Wu, Quantifying the Energy Cost of Data Movement for Emerging Smart Phone Workloads on Mobile Platforms, IEEE International Symposium on Workload Characterization (IISWC), pp.171-180, 2014.

D. Pandiyan, S. Lee, and C. Wu, Performance, Energy Characterizations and Architectural Implications of An Emerging Mobile Platform Benchmark Suite -MobileBench, IEEE International Symposium on Workload Characterization (IISWC), pp.133-142, 2013.

Y. Huang, Z. Zha, M. Chen, and L. Zhang, Moby: A Mobile Benchmark Suite for Architectural Simulators, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp.45-54, 2014.

A. Gutierrez, R. G. Dreslinski, T. F. Wenisch, T. Mudge, A. Saidi et al., Full-System Analysis and Characterization of Interactive Smartphone Applications, IEEE International Symposium on Workload Characterization (IISWC), pp.81-90, 2011.

G. Bournoutian and A. Orailoglu, Application-Aware Adaptive Cache Architecture for Power-Sensitive Mobile Processors, ACM Transactions on Embedded Computing Systems (TECS), vol.13, issue.3, p.26, 2013.

G. Madalozzo, L. Duenha, R. Azevedo, and F. G. Moraes, Scalability Evaluation in Many-core Systems due to the Memory Organization, IEEE International Conference on Electronics, Circuits and Systems (ICECS), pp.396-399, 2016.

S. Ma, M. Huang, E. Cartwright, and D. Andrews, Scalable Memory Hierarchies for Embedded Manycore Systems, International Conference on Reconfigurable Computing: Architectures, Tools and Applications (ARC), pp.151-162, 2012.

. Gartner, Gartner Says Worldwide Device Shipments Will Increase 2 Percent in 2018, Reaching Highest Year-Over-Year Growth Since, 2015.

K. T. Cheng, X. Yang, and Y. Wang, Performance Optimization of Vision Apps on Mobile Application Processor, International Conference on Systems, Signals and Image Processing (IWSSIP), pp.187-191, 2013.

B. K. Reddy, A. K. Singh, D. Biswas, G. V. Merrett, and B. M. Al-hashimi, Intercluster Thread-to-core Mapping and DVFS on Heterogeneous Multi-cores, IEEE Transactions on Multi-Scale Computing Systems, issue.99, pp.1-14, 2017.

S. A. Khanjari and W. Vanderbauwhede, Evaluation of the Memory Communication Traffic in a Hierarchical Cache Model for Massively-Manycore Processors, Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP), pp.726-733, 2016.

K. Yan and X. Fu, Energy-Efficient Cache Design in Emerging Mobile Platforms: The Implications and Optimizations, IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.375-380, 2015.

L. Alvarez, L. Vilanova, M. Moreto, M. Casas, M. Gonzalez et al., Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures, ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.720-732, 2015.

M. Shoushtari and N. Dutt, SAM: Software-Assisted Memory Hierarchy for Scalable Manycore Embedded Systems, IEEE Embedded Systems Letters, vol.9, issue.4, pp.109-112, 2017.

M. Ceriani, S. Secchi, O. Villa, A. Tumeo, and G. Palermo, Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures, IEEE Transactions on Parallel and Distributed Systems, vol.28, issue.6, pp.1635-1648, 2017.

J. Hascoët, K. Desnos, J. F. Nezan, and B. D. Dinechin, Hierarchical Dataflow Model for efficient programming of clustered manycore processors, IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), pp.137-142, 2017.

O. J. On and F. A. Hussin, Evaluation and performance analysis of heterogeneous multicore cluster processor architecture, International Conference on Frontiers of Communications, Networks and Applications (ICFCNA), pp.1-6, 2014.

M. R. Kakoee, V. Petrovic, and L. Benini, A multi-banked shared-l1 cache architecture for tightly coupled processor clusters, International Symposium on System on Chip (SoC), pp.1-5, 2012.

H. Esmaeilzadeh, E. Blem, R. Amant, . St, K. Sankaralingam et al., Dark Silicon and the End of Multicore Scaling, ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.365-376, 2011.

S. Borkar, Thousand core chips: A technology perspective, IEEE Design Automation Conference (DAC), pp.746-749, 2007.

N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi et al., The gem5 Simulator, ACM SIGARCH Computer Architecture News, vol.39, issue.2, pp.1-7, 2011.

A. Gutierrez, J. Pusdesris, R. Dreslinski, T. Mudge, C. Sudanthi et al., Sources of error in full-system simulation, IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), pp.13-22, 2014.

F. Endo, D. Courousse, and H. Charles, Micro-architectural simulation of in-order and out-of-order arm microprocessors with gem5, International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), pp.266-273, 2014.
URL : https://hal.archives-ouvertes.fr/cea-01817868

A. Butko, A. Gamatié, G. Sassatelli, L. Torres, and M. Robert, Design Exploration for next Generation High-Performance Manycore On-chip Systems: Application to big.LITTLE Architectures, IEEE Computer Society Annual Symposium on VLSI, pp.551-556, 2015.
URL : https://hal.archives-ouvertes.fr/lirmm-01255927

A. Butko, R. Garibotti, L. Ost, V. Lapotre, A. Gamatié et al., A trace-driven approach for fast and accurate simulation of manycore architectures, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.707-712, 2015.
URL : https://hal.archives-ouvertes.fr/lirmm-01255921

R. A. Uhlig, 28 ARM: "Cortex-A series processors -A Technical Reference Manual, 1995.

. Samsung, Exynos 4 Quad News Roundup, 2012.

J. E. Stine, I. Castellanos, M. Wood, J. Henson, F. Love et al., FreePDK: an open-source variation-aware design kit, IEEE International Conference on Microelectronic Systems Education, pp.173-174, 2007.

S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg et al., A network on chip architecture and design methodology, IEEE Computer Society Annual Symposium on VLSI, pp.117-124, 2002.

X. Dong, C. Xu, Y. Xie, and N. P. Jouppi, NVSim: a circuit-level performance, energy, and area model for emerging nonvolatile memory, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol.31, issue.7, pp.994-1007, 2012.

S. C. Woo, M. Ohara, E. Torrie, J. P. Singh, and A. Guptat, The splash-2 programs: characterization and methodological considerations, ACM/IEEE International Symposium on Computer Architecture (ISCA), pp.24-36, 1995.

R. Garibotti, L. Ost, R. Busseuil, M. Kourouma, C. Adeniyi-jones et al., Simultaneous Multithreading Support in Embedded Distributed Memory MPSoCs, IEEE Design Automation Conference (DAC), pp.1-7, 2013.
URL : https://hal.archives-ouvertes.fr/lirmm-01391168

J. Hu and R. Marculescu, Energy-aware mapping for tile-based NoC architectures under performance constraints, Asia and South Pacific Design Automation Conference (ASP-DAC), pp.233-239, 2003.

D. M. Brooks, P. Bose, S. E. Schuster, H. Jacobson, P. N. Kudva et al., Power-aware microarchitecture: design and modeling challenges for next-generation microprocessors, IEEE Micro, vol.20, issue.6, pp.26-44, 2000.