P. Batude, Sequential Integration: A Key Enabling Technology for Heterogeneous Co-Integration of New Function With CMOS, IEEE J. Emerging and Selected Topics in Circuits and Sys, vol.2, issue.4, pp.714-722, 2012.

K. Chang, Design Automation and Testing of Monolithic 3D ICs: Opportunities, Challenges, and Solutions, ICCAD, pp.805-810, 2017.

A. Koneru, Impact of Electrostatic Coupling and WaferBonding Defects on Delay Testing of Monolithic 3D Integrated Circuits, J. Emerg. Technol. Comput. Syst, 2017.

K. Chang, Frequency and Time Domain Analysis of Power Delivery Network for Monolithic 3D ICs, ISLPED, 2017.

S. K. Samal, Full Chip Impact Study of Power Delivery Network Designs in Gate-Level Monolithic 3-D ICs, TCAD, vol.36, issue.6, pp.992-1003, 2017.

S. Panth, Tier-partitioning for Power Delivery vs Cooling Tradeoff in 3D VLSI for Mobile Applications, DAC, vol.92, pp.1-92, 2015.

S. Ravi, Power-Aware Test: Challenges and Solutions, ITC, pp.1-10, 2007.

P. Girard, Power-Aware Testing and Test Strategies for Low Power Devices, 2009.
URL : https://hal.archives-ouvertes.fr/lirmm-00371356

N. James, Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor, International SolidState Circuits Conference, 2007.

O. Billoint, A comprehensive study of Monolithic 3D cell on cell design using commercial 2D tool, DATE, 2015.

S. Panth, Design and CAD Methodologies for Low Power Gate-Level Monolithic 3D ICs, ISLPED, pp.171-176, 2014.

Y. J. Lee and S. K. Lim, Co-Optimization and Analysis of Signal, Power, and Thermal Interconnects in 3-D ICs, IEEE Trans. CAD, vol.30, issue.11, pp.1635-1648, 2011.

S. Das, Modeling and characterization of the system-level Power Delivery Network for a dual-core ARM Cortex-A57 cluster in 28nm CMOS, ISLPED, pp.146-151, 2015.

X. Huang, Physics-Based Electromigration Models and FullChip Assessment for Power Grid Networks, vol.35, pp.1848-1861, 2016.

I. A. Blech, Electromigration in thin aluminum films on titanium nitride, Journal of Applied Physics, vol.47, issue.4, pp.1203-1208, 1976.

H. Cook and K. Skadron, Predictive design space exploration using genetically programmed response surfaces, DAC, 2008.

S. Panth, Shrunk-2-D: A Physical Design Methodology to Build Commercial-Quality Monolithic 3-D ICs, TCAD, vol.36, issue.10, pp.1716-1724, 2017.

S. Panth, Placement-Driven Partitioning for Congestion Mitigation in Monolithic 3D IC Designs, IEEE Trans. CAD, vol.34, issue.4, pp.540-553, 2015.

A. Ramalingam, Robust analytical gate delay modeling for low voltage circuits, ASPDAC, vol.6, 2006.