ExaScale Computing Study: Technology Challenges in, Study Lead, 2008. ,
Efficiency modeling and exploration of 64-bit arm compute nodes for exascale, Microprocess. Microsyst, vol.53, issue.C, pp.68-80, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01586191
Emerging nvm: A survey on architectural integration and research challenges, ACM Trans. Des. Autom. Electron. Syst, vol.23, issue.2, pp.1-14, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01709571
Cavium Announces GA for ThunderX2 ,
, , 2018.
Skylake-sp: A 14nm 28-core xeon R processor, Solid-State Circuits Conference-(ISSCC), pp.34-36, 2018. ,
DOI : 10.1109/isscc.2018.8310170
High-performance conjugate-gradient benchmark, Int. J. High Perform. Comput. Appl, vol.30, issue.1, pp.3-10, 2016. ,
Comparative benchmarking of the first generation of hpc-optimised arm processors on isambard, Cray User Group, vol.5, 2018. ,
Sparc64 xifx: Fujitsu's next-generation processor for high-performance computing, vol.35, pp.6-14, 2015. ,
DOI : 10.1109/mm.2015.11
Fujitsu Reveals Details of Processor That Will Power Post-K Supercomputer, 2018. ,
Huawei Unveils Industry's Highest-Performance ARMbased CPU, 2019. ,
Opportunities and challenges of emerging memory technologies, 2017. ,
Disaggregated memory for expansion and sharing in blade servers, SIGARCH Comput. Archit. News, vol.37, issue.3, pp.267-278, 2009. ,
DOI : 10.1145/1555754.1555789
Research problems and opportunities in memory systems, Supercomput. Front. Innov.: Int. J, vol.1, issue.3, pp.19-55, 2014. ,
Energy management for commercial servers, Computer, vol.36, issue.12, pp.39-48, 2003. ,
DOI : 10.1109/mc.2003.1250880
Dram refresh mechanisms, penalties, and trade-offs, IEEE Trans. Comput, vol.65, issue.1, pp.108-121, 2016. ,
DOI : 10.1109/tc.2015.2417540
Spintronics based random access memory: a review, Materials Today, vol.20, issue.9, pp.530-548, 2017. ,
Exploring mram technologies for energy efficient systems-on-chip, IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol.6, issue.3, pp.279-292, 2016. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01419429
Embedded systems to high performance computing using stt-mram, Design, Automation Test in Europe Conference Exhibition, pp.536-541, 2017. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01548996
Compile-time silent-store elimination for energy efficiency: an analytic evaluation for non-volatile cache memory, Proceedings of the RAPIDO 2018 Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools ,
URL : https://hal.archives-ouvertes.fr/hal-01660686
, , vol.5, pp.1-5, 2018.
Static prediction of silent stores, TACO, vol.15, issue.4, pp.1-44, 2019. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01912634
Improving the performance of STT-MRAM LLC through enhanced cache replacement policy, Architecture of Computing Systems -ARCS 2018 -31st International Conference, vol.10793, pp.168-180, 2018. ,
,
Energy-efficient memory mappings based on partial wcet analysis and multi-retention time stt-ram, Proceedings of the 26th International Conference on Real-Time Networks and Systems, ser. RTNS '18, pp.148-158, 2018. ,
URL : https://hal.archives-ouvertes.fr/hal-01871320
Composing lifetime enhancing techniques for non-volatile main memories, Proceedings of the International Symposium on Memory Systems, ser. MEMSYS '17, pp.363-373, 2017. ,
Nonvolatile and reprogrammable, the read-mostly memory is here, Electronics, vol.43, issue.20, pp.56-60, 1970. ,
Demonstration of reliable triple-levelcell (TLC) phase-change memory, Proceedings of the International Memory Workshop (IMW), pp.1-4, 2016. ,
Intel and Micron Produce Breakthrough Memory Technology, 2017. ,
Resistive random access memory (reram) based on metal oxides, Proceedings of the IEEE, vol.98, issue.12, pp.2237-2251, 2010. ,
UMC is a foundry partner for Panasonic in making Resistive RAM, 2017. ,
, MB3 D3.7-Final-Report-on-Memory-Hierarchy-Investigation-1.pdf, MontBlanc 3 project, 2018.
, The gem5 simulator, 2016.
Nvmain 2.0: A user-friendly memory simulator to model (non-)volatile memory systems, Computer Architecture Letters, vol.14, issue.2, pp.140-143, 2015. ,
,
, 1&ved=0ahUKEwif55DcxtDbAhUKVxQKHbsiBaAQFggoMAA&url= https%3A%2F%2Fwww.micron.com%2F ? %2Fmedia%2Fdocuments% 2Fproducts%2Fdata-sheet%2Fmodules%2Frdimm%2Fddr4% 2Fasf18c2gx72pdz.pdf&usg=AOvVaw1YvGKpxb5Aok0KYGnbhwrE, 2015.
Phase-change technology and the future of main memory, IEEE micro, vol.30, issue.1, 2010. ,
A case for small row buffers in nonvolatile main memories, Proceedings of the International Conference on Computer Design (ICCD), pp.484-485, 2012. ,
Evaluating stt-ram as an energy-efficient main memory alternative, Proceedings of the International Symposium on Performance Analysis of Systems and Software (ISPASS), pp.256-267, 2013. ,
Row buffer locality aware caching policies for hybrid memories, Proceedings of the International Conference on Computer Design (ICCD), pp.337-344, 2012. ,
Architecting a hardware-managed hybrid dimm optimized for cost/performance, Proceedings of the International Symposium on Memory Systems, ser. MEMSYS '18, pp.327-340, 2018. ,
Efficiently enabling conventional block sizes for very large die-stacked dram caches, Proceedings of the International Symposium on Microarchitecture, pp.454-464, 2011. ,
Enabling efficient and scalable hybrid memories using fine-granularity dram cache management, IEEE Computer Architecture Letters, vol.11, issue.2, pp.61-64, 2012. ,
A case for efficient hardware/software cooperative management of storage and memory, Proceedings of the Workshop on Energy-Efficient Design, pp.1-7, 2013. ,
Firm: Fair and high-performance memory control for persistent memory systems, Proceedings of the International Symposium on Microarchitecture, pp.153-165, 2014. ,
Design exploration for next generation high-performance manycore on-chip systems: Application to big.little architectures, 2015 IEEE Computer Society Annual Symposium on VLSI, pp.551-556, 2015. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01255927
Full-system simulation of big.little multicore architecture for performance and energy exploration," in MCSoC, pp.201-208, 2016. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01418745
Dramsim2: A cycle accurate memory system simulator, IEEE Computer Architecture Letters, vol.10, issue.1, pp.16-19, 2011. ,
Dramsys: A flexible dram subsystem design space exploration framework, IPSJ Transactions on System LSI Design Methodology, vol.8, pp.63-74, 2015. ,
Ramulator: A fast and extensible dram simulator, IEEE Computer Architecture Letters, vol.15, issue.1, pp.45-49, 2016. ,
A 20 nm 1.8 V 8 Gb PRAM with 40 MB/s program bandwidth, Proceedings of the International SolidState Circuits Conference, pp.46-48, 2012. ,
An 8 Mb multilayered cross-point ReRAM macro with 443 MB/s write throughput, Proceedings of the International Solid-State Circuits Conference, pp.432-434, 2012. ,
Nvsim: A circuit-level performance, energy, and area model for emerging nonvolatile memory, IEEE Transactions on, vol.31, issue.7, pp.994-1007, 2012. ,
Destiny: A comprehensive tool with 3d and multi-level cell memory modeling capability, Journal of Low Power Electronics and Applications, vol.7, issue.3, 2017. ,
URL : https://hal.archives-ouvertes.fr/hal-01609132
Architecting phase change memory as a scalable dram alternative, SIGARCH Comput ,
, , vol.37, pp.2-13, 2009.
After hard driveswhat comes next?, IEEE Transactions on Magnetics, vol.45, pp.3406-3413, 2009. ,
Exsom board, 2016. ,
lmbench: Portable Tools for Performance Analysis, USENIX annual technical conference, pp.279-294, 1996. ,
Cacti 6.0: A tool to model large caches, 2009. ,
The parsec benchmark suite: Characterization and architectural implications, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT), pp.72-81, 2008. ,
Experiences with mobile processors for energy efficient hpc, Proceedings of the Conference on Design, Automation and Test in Europe, ser. DATE '13, pp.464-468, 2013. ,
,
, , pp.165-223, 2018.
Hydrodynamics challenge problem, Tech. Rep, 2011. ,
The linpack benchmark: Past, present, and future. concurrency and computation: Practice and experience, Concurrency and Computation: Practice and Experience, vol.15, p.2003, 2003. ,
Row buffer locality aware caching policies for hybrid memories, Proceedings of the 2012 IEEE 30th International Conference on Computer Design ,
, , pp.337-344, 2012.
Ompss: a proposal for programming heterogeneous multi-core architectures, Parallel Processing Letters, vol.21, issue.2, pp.173-193, 2011. ,
Criticality-aware dynamic task scheduling for heterogeneous architectures, Proceedings of the 29th ACM on International Conference on Supercomputing, ser. ICS '15, pp.329-338, 2015. ,
Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSs, OpenSuCo 1 (ISC17), 2017. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01723762