, Reg1:=PI(TP1)
, , vol.2
, Reg5:=MULT1
, /*Reg5 memorizes MULT1's test response (TR)*/ Reg2:=PI
, , p.6
, , p.3
,
Synthesis of testable finite state machine, Proc. ISCAS, pp.3114-3115, 1990. ,
A Partial Scan Method for Sequential Circuits with Feedback, IEEE Transactions on Computers, vol.39, pp.544-548, 1990. ,
On Determining Scan Flip-Flops in Partial Scan Designs, pp.322-325, 1990. ,
High-Level Synthesis of Testable Design: An Overview of University Systems, proc. ITC, Test Synthesis Seminar, Digest of Papers, pp.1-8, 1994. ,
Micro-architectural Synthesis of VLSI Designs with High Test Concurrency, pp.206-211, 1994. ,
SYNTEST: a method for high-level SYNthesis with self-TESTability, pp.458-462, 1991. ,
Allocation and Assignment in High-Level Synthesis for Self-Testable Data-Paths, pp.463-472, 1991. ,
Genesis: A Behavioral Synthesis for Hierarchical Testability, pp.272-276, 1994. ,
Behavioral Synthesis of Testable Designs, pp.436-445, 1994. ,
Behavioral Synthesis for Easy Testability in Data Path Allocation, proc. ICCD, pp.29-32, 1992. ,
Incorporating Testability Considerations in High-Level Synthesis, IEEE J. of Electronic Testing, pp.43-55, 1994. ,
A Stepwise Refinement DataPath Synthesis Procedure for Easy Testability, proc. ETC, pp.586-590, 1994. ,
Structural and Behavioral Synthesis for Testability Techniques, IEEE Trans. CAD, vol.13, issue.6, pp.777-785, 1994. ,
Transforming behavioral specifications to facilitate synthesis of testable designs, pp.184-193, 1994. ,
Conditional resource sharing method for behavioral synthesis of highly testable data paths, pp.744-753, 1993. ,
Exploiting Hardware Sharing in High-Level Synthesis for Partial Scan Optimization, pp.20-25, 1993. ,
Behavioral synthesis of Area-Efficient Testable Designs using interaction between Hardware Sharing and Partial Scan, IEEE Transactions on CAD, vol.14, issue.9, pp.1141-1154, 1995. ,
Behavioral Synthesis for Highly Testable Data Paths under Non-Scan and PartialScan Environments, pp.292-297, 1993. ,
Synthesis of Self-Testable Controllers, pp.580-585, 1994. ,
A knowledge-based System for Designing Testable VLSI chips, IEEE Design&Test, pp.56-68, 1985. ,
Test Generation for Data-Path Logic: The F-path method, IEEE Journal of Solid State circuits, vol.23, issue.2, pp.421-427, 1988. ,
Testability and architectural synthesis of digital circuits, 1995. ,
Scheduling and binding algorithm for high level synthesis, pp.1-6, 1989. ,
A new method for the minimization of memory related area, pp.184-189 ,
High Level Synthesis for Easy Testability, pp.198-206, 1995. ,
Automated Synthesis of Data Paths in Digital Systems, IEEE Transactions on CAD, vol.5, 1986. ,
Experience with ADAM synthesis system, pp.56-61, 1989. ,
Parallel and pipelined VLSI implementation of signal processing algorithms, VLSI and Modern Signal Processing, pp.257-260 ,
, Sunrise tests system: "Testgen" reference manual. Version2.1, 1994.
, , 1992.