, Listing all the registers in the circuit and choosing a random one to inject a fault in it

K. H. Walters, S. H. Gerez, G. J. Smit, S. Baillou, G. K. Rauwerda et al., Multicore SoC for on-board payload signal processing, Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS), pp.17-21, 2011.

D. J. Sorin, Fault Tolerant Computer Architecture, 2009.

D. Bertozzi, The Data-Link Layer in NoC Design, Networks on Chips: Technology and Tools

G. Micheli and L. Benini, , 2006.

P. Guerrier and A. Greiner, A scalable architecture for system-on-chip interconnections, Proceedings of the 2nd Sophia Antipolis Forum on MicroElectronics (SAME), pp.90-93, 1999.
URL : https://hal.archives-ouvertes.fr/hal-01574082

W. J. Dally and B. Towles, Route packets, not wires: On-chip interconnection networks, Proceedings of the 38th Design Automation Conference (DAC), pp.684-689, 2001.

L. Benini and G. De-micheli, Networks on chip: a new paradigm for systems on chip design, Proceedings of the 2002 Design, Automation and Test in Europe Conference and Exhibition, pp.4-8, 2002.

A. Jantsch, Networks on chip, vol.396, 2003.

C. A. Zeferino and A. A. Susin, SoCIN: a parametric and scalable network-on-chip, Proceedings of the 16th Symposium on Integrated Circuits Syst. Design, pp.169-174, 2003.

J. Duato, S. Yalamanchili, and L. M. Ni, Interconnection Networks: An Engineering Approach

M. Kaufmann, , 2003.

W. J. Dally and B. P. Towles, Principles and Practices of Interconnection Networks, 2004.

D. R. Melo, C. A. Zeferino, L. Dilillo, and E. A. Bezerra, Analyzing the Error Propagation in a Parameterizable Network-on-Chip Router, Proceedings of the 2019 IEEE Latin American Test Symposium (LATS), pp.1-6, 2019.
URL : https://hal.archives-ouvertes.fr/lirmm-02008414

T. Bjerregaard and S. Mahadevan, A survey of research and practices of network-on-chip, ACM Comput. Surv, vol.38, 2006.

A. W. Topol, D. La-tulipe, L. Shi, D. J. Frank, K. Bernstein et al., Three-dimensional integrated circuits. IBM J. Res. Dev, vol.50, pp.491-506, 2006.

N. E. Jerger and L. S. Peh, On-chip networks, Synth. Lect. Comput. Archit, vol.4, pp.1-141, 2009.

A. Scionti, S. Mazumdar, and A. Portero, Towards a scalable software defined network-on-chip for next generation cloud, Sensors, vol.18, 2018.

A. Avizienis, J. C. Laprie, B. Randell, and C. Landwehr, Basic concepts and taxonomy of dependable and secure computing, IEEE Trans. Dependable Secur. Comput, vol.1, pp.11-33, 2004.

C. Constantinescu, Trends and challenges in VLSI circuit reliability, IEEE Micro, vol.23, pp.14-19, 2003.

H. Zimmer and A. Jantsch, A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip, Proceedings of the First IEEE/ACM/IFIP International Conference on

, Hardware/Software Codesign and Systems Synthesis, pp.1-3, 2003.

A. P. Frantz, F. L. Kastensmidt, L. Carro, and E. Cota, Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk, Proceedings of the 2006 IEEE International Test Conference, pp.1-9, 2006.

D. Park, C. Nicopoulos, J. Kim, N. Vijaykrishnan, and C. R. Das, Exploring fault-tolerant network-on-chip architectures, Proceedings of the International Conference on Dependable Systems and Networks, pp.93-104, 2006.

A. Kohler, G. Schley, and M. Radetzki, Fault tolerant network on chip switching with graceful performance degradation, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol.29, pp.883-896, 2010.

H. Bokhari, H. Javaid, M. Shafique, J. Henkel, S. Parameswaran et al., Multimode interconnect architecture for manycore chips, Proceedings of the 2015 52nd ACM/EDAC/IEEE Design Automation Conference, pp.1-6, 2015.

T. F. Pereira, D. R. De-melo, E. A. Bezerra, and C. A. Zeferino, Mechanisms to Provide Fault Tolerance to a Network-on-Chip, IEEE Lat. Am. Trans, vol.15, pp.1034-1042, 2017.

É. Cota, F. L. Kastensmidt, M. Cassel, M. Herve, P. Almeida et al., A high-fault-coverage approach for the test of data, control and handshake interconnects in mesh networks-on-chip, IEEE Trans. Comput, vol.57, pp.1202-1215, 2008.

S. Tosun, V. B. Ajabshir, O. Mercanoglu, and O. Ozturk, Fault-tolerant topology generation method for application-specific network-on-chips, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol.34, pp.1495-1508, 2015.

C. Chen, Y. Fu, and S. Cotofana, Towards Maximum Utilization of Remained Bandwidth in Defected NoC Links, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol.36, pp.285-298, 2017.

I. Loi, F. Angiolini, S. Fujita, S. Mitra, and L. Benini, Characterization and implementation of fault-tolerant vertical links for 3-D networks-on-chip, IEEE Trans. on Comput.-Aided Des. Integr. Circuits Syst, vol.30, pp.124-134, 2011.

A. M. Rahmani, P. Liljeberg, K. Latif, J. Plosila, K. R. Vaddina et al., Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures, Proceedings of the Fifth ACM/IEEE International Symposium, pp.65-72, 2011.

A. Eghbal, P. M. Yaghini, N. Bagherzadeh, and M. Khayambashi, Analytical fault tolerance assessment and metrics for tsv based 3D network-on-chip, IEEE Trans. Comput, vol.64, pp.3591-3604, 2015.

C. Feng, Z. Lu, A. Jantsch, M. Zhang, and Z. Xing, Addressing transient and permanent faults in NoC with efficient fault-tolerant deflection router, IEEE Trans. Very Large Scale Integr. Syst, vol.21, pp.1053-1066, 2013.

S. Pasricha and Y. Zou, A low overhead fault tolerant routing scheme for 3D Networks-on-Chip, Proceedings of the 2011 12th International Symposium on Quality Electronic Design, pp.1-8, 2011.

S. Manolache, P. Eles, and Z. Peng, Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC, Proceedings of the 42nd Design Automation Conference, pp.266-269, 2005.

O. Derin, D. Kabakci, and L. Fiorin, Online task remapping strategies for fault-tolerant network-on-chip multiprocessors, Proceedings of the Fifth ACM/IEEE International Symposium, pp.129-136, 2011.

Y. C. Chang, C. T. Chiu, S. Y. Lin, and C. K. Liu, On the design and analysis of fault tolerant NoC architecture using spare routers, Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.431-436, 2011.

C. L. Chou and R. Marculescu, FARM: Fault-aware resource management in NoC based multiprocessor platforms, Proceedings of the 2011 Design, Automation and Test in Europe, pp.1-6, 2011.

H. Kariniemi and J. Nurmi, NoC Interface for fault-tolerant Message-Passing communication on Multiprocessor SoC platform, Proceedings of the 2009 NORCHIP, pp.1-6, 2009.

L. Fiorin and M. Sami, Fault-tolerant network interfaces for networks-on-Chip, IEEE Trans. Dependable Secur. Comput, vol.11, pp.16-29, 2014.

V. Fochi, E. Wächter, A. Erichsen, A. M. Amory, and F. G. Moraes, An integrated method for implementing online fault detection in NoC based MPSoCs, Proceedings of the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1562-1565, 2015.

A. Prodromou, A. Panteli, C. Nicopoulos, and Y. Sazeides, Nocalert: An on-line and real-time fault detection mechanism for network-on-chip architectures, Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture, pp.60-71, 2012.

T. Schonwald, J. Zimmermann, O. Bringmann, and W. Rosenstiel, Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures, Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp.527-534, 2007.

Z. Zhang, A. Greiner, and S. Taktak, A reconfigurable routing algorithm for a fault-tolerant 2D-mesh network-on-chip, Proceedings of the 2008 45th ACM/IEEE Design Automation Conference, pp.441-446, 2008.
URL : https://hal.archives-ouvertes.fr/hal-00591783

S. Jovanovic, C. Tanougast, S. Weber, and C. Bobda, A new deadlock-free fault-tolerant routing algorithm for NoC interconnections, Proceedings of the 2009 International Conference on Field Programmable Logic and Applications, pp.326-331, 2009.
URL : https://hal.archives-ouvertes.fr/hal-02065678

D. M. Ancajas, K. Bhardwaj, K. Chakraborty, and S. Roy, Wearout resilience in NoCs through an aging aware adaptive routing algorithm, IEEE Trans. Very Large Scale Integr. Syst, vol.23, pp.369-373, 2015.

J. Liu, J. Harkin, Y. Li, and L. P. Maguire, Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead, IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst, vol.35, pp.260-273, 2016.

P. Ren, X. Ren, S. Sane, M. A. Kinsy, and N. Zheng, A deadlock-free and connectivity-guaranteed methodology for achieving fault-tolerance in on-chip networks, IEEE Trans. Comput, vol.65, pp.353-366, 2016.

M. Ebrahimi, M. Daneshtalab, and J. Plosila, Fault-tolerant routing algorithm for 3D NoC using Hamiltonian path strategy, Proceedings of the 2013 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.1601-1604, 2013.

E. Wachter, A. Erichsen, A. Amory, and F. Moraes, Topology-agnostic fault-tolerant NoC routing method, Proceedings of the 2013 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.1595-1600, 2013.

S. Murali, D. Atienza, L. Benini, and G. De-michel, A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip, Proceedings of the 43rd annual Design Automation Conference, pp.845-848, 2006.

A. Pullini, F. Angiolini, D. Bertozzi, and L. Benini, Fault tolerance overhead in network-on-chip flow control schemes, Proceedings of the 2005 18th Symposium on Integrated Circuits and Systems Design, pp.224-229, 2005.

W. C. Tsai, D. Y. Zheng, S. J. Chen, and Y. H. Hu, A fault-tolerant NoC scheme using bidirectional channel, Proceedings of the 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC), pp.918-923, 2011.

M. Koibuchi, H. Matsutani, H. Amano, and T. M. Pinkston, A lightweight fault-tolerant mechanism for network-on-chip, Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip, pp.13-22, 2008.

M. C. Meyer, A. B. Ahmed, Y. Okuyama, and A. B. Abdallah, Fttdor: Microring fault-resilient optical router for reliable optical network-on-chip systems, Proceedings of the 2015 IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, pp.227-234, 2015.

M. O. Agyeman, K. F. Tong, and T. Mak, Towards reliability and performance-aware wireless network-on-chip design, Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp.205-210, 2015.

M. Radetzki, C. Feng, X. Zhao, and A. Jantsch, Methods for fault tolerance in networks-on-chip, ACM Comput. Surv, vol.46, 2013.

C. Marcon, A. Amory, T. Webber, T. Volpato, and L. B. Poehls, Phoenix NoC: A distributed fault tolerant architecture, Proceedings of the 2013 IEEE 31st International Conference on Computer Design (ICCD), pp.7-12, 2013.

C. Grecu, A. Ivanov, R. Saleh, E. S. Sogomonyan, and P. P. Pande, On-line fault detection and location for NoC interconnects, Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS'06), p.6, 2006.

L. Wang, S. Ma, C. Li, W. Chen, and Z. Wang, A high performance reliable NoC router, vol.58, pp.583-592, 2017.

R. Bishnoi, V. Laxmi, M. S. Gaur, and J. Flich, 2-LBDR: distance-driven routing to handle permanent failures in 2D mesh NOCs, Proceedings of the 2015 Design, Automation and Test in Europe Conference and Exhibition (DATE), pp.800-805, 2015.

H. Ziade, R. A. Ayoubi, and R. Velazco, A survey on fault injection techniques, Int. Arab J. Inf. Technol, vol.1, pp.171-186, 2004.
URL : https://hal.archives-ouvertes.fr/hal-00105562

R. Travessini, P. R. Villa, F. L. Vargas, and E. A. Bezerra, Processor core profiling for SEU effect analysis, Proceedings of the 2018 IEEE 19th Latin-American Test Symposium (LATS), pp.1-6, 2018.

D. R. Melo, C. A. Zeferino, L. Dilillo, E. A. Bezerra, and . Xarc-extensible-architecture, , p.27, 2019.