In this paper we place ourselves in the setting of formal representation of functional specifications given in logical diagrams (LD) for verification and test purposes. Our contribution consists in defining a formal structure that explicitly encodes the semantics and behavior of a LD. We put in a complete transformation procedure of the non-formal LD specifications into a directed state graph such that properties like oscillatory behavior become formally verifiable on LDs. We motivate and illustrate our approach with a scenario inspired from a real world power plant specification.