Testing Logical Diagrams in Power Plants: A Tale of LTL Model Checking - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2023

Testing Logical Diagrams in Power Plants: A Tale of LTL Model Checking

Abstract

In this paper, we focus on the application of LTL (Linear Temporal Logic) model checking on logical diagrams (LD), which are a type of functional specification used for logical controllers in many nuclear power plants. The goal is to check properties on LDs and to generate counter examples serving as validation tests for logical controllers. We propose a sound and complete LTL encoding framework for LDs allowing the use of model checking (MC) and evaluate different MC techniques on real world LD to efficiently generate counterexamples for verifiable properties.

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Dates and versions

lirmm-04214807 , version 1 (22-09-2023)

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Aziz Sfar, David Carral, Dina Irofti, Madalina Croitoru. Testing Logical Diagrams in Power Plants: A Tale of LTL Model Checking. FMICS 2023 - Formal Methods for Industrial Critical Systems, Sep 2023, Antwerp, Netherlands. pp.189-204, ⟨10.1007/978-3-031-43681-9_11⟩. ⟨lirmm-04214807⟩
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