Analysis of Resistive-Open Defects on a Foundry 8T SRAM-based IMC Architecture - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2023

Analysis of Resistive-Open Defects on a Foundry 8T SRAM-based IMC Architecture

Abstract

The adoption of In-Memory Computing (IMC) architectures is one of the promising approaches to efficiently solve the Von Neumann bottleneck problem. In addition to arithmetic operations, IMC architectures aim at integrating additional logic operations directly in the memory array or/and at the periphery for saving time and power consumption. In this paper, a comprehensive model of a 128x128 bitcell array based on a 28nm FD-SOI process technology has been considered to analyze the behavior of IMC 8T SRAM bitcells in the presence of resistive-open defects injected in the read port. A hierarchical analysis including a detailed study of each defect was performed in order to determine their impact both in memory and computing modes, both locally on the defective bitcell and globally on the array. Experimental results show that the IMC mode offers the most effective detectability of resistive-open defects.
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Dates and versions

lirmm-04565688 , version 1 (02-05-2024)

Identifiers

  • HAL Id : lirmm-04565688 , version 1

Cite

Lila Ammoura, Marie-Lise Flottes, Patrick Girard, Jean-Philippe Noël, Arnaud Virazel. Analysis of Resistive-Open Defects on a Foundry 8T SRAM-based IMC Architecture. 17e Colloque National du GDR SoC², Jun 2023, Lyon, France. ⟨lirmm-04565688⟩
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