Conference Papers Year : 2024

IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications

Aibin Yan
Chen Dong
Xing Guo
Jie Song
Jie Cui
Tianming Ni
Xiaoqing Wen

Abstract

Modern powerful CMOS chips are usually highly integrated and implemented with aggressively shrunk technology nodes. In radiation environment, under charge-sharing mechanism, one particle striking can simultaneously impact multiple nodes causing double-node-upsets (DNUs) and triple-node-upsets (TNUs). In this paper, we propose an Interlocked Dual-circle Latch Design, namely IDLD, with low cost and TNU recovery for aerospace applications. IDLD consists of four transmission gates and twelve 2-input Celements (CEs) implemented in 22nm CMOS process. Simulation results demonstrate the complete TNU recovery as well as costeffectiveness for the proposed IDLD latch.
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Dates and versions

lirmm-04738332 , version 1 (15-10-2024)

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Aibin Yan, Chen Dong, Xing Guo, Jie Song, Jie Cui, et al.. IDLD: Interlocked Dual-Circle Latch Design with Low Cost and Triple-Node-Upset-Recovery for Aerospace Applications. GLSVLSI 2024 - ACM Great Lakes Symposium on VLSI, Jun 2024, Clearwater, FL, United States. pp.19-24, ⟨10.1145/3649476.3658761⟩. ⟨lirmm-04738332⟩
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