, Code analysis methodology to characterize the termination probability of an application affected by a SEU in the binary code An environment for fault injection based on a ethernet router in Linux ? Stefano Palazzo (2004): an ATPG for balancing the power consumption during the burn-in test Control Flow checking to protect microprocessors against radiations ? Paolo Pellegrino A watchdog process to increase the reliability of computer systems ? Gianfranco Panico Self-Repair of FIR Filters ? G Trusted Flow to protect against soft errors ? Bottigliero Davide, Vezza, 2003.
, Audio/Visual remote systems using RTP protocol ? Ahmed El Boujouf A masking approach to protect AES against Identification of optimal input sequences for A fast approach for the identification of correlation between power and data ? Vincent Gregot Study and implementation of an attack platform for DPA ? Driss Aboulkassimi Validation of an optimization method for DPA attacks ? Miro Valka): Development of a tool for enhancing the resolution of the Testing identical dies in 3D stacked Integrated Circuits ? Chloé Desdouits (2012): Implementation of an optimal algorithm for Wafer to Wafer matching ? Artem Marisov (2013): Implementation of a TMR scheme at flip-flop level Chapter II: Details Habilitation à Diriger les Recherches -Giorgio Di Natale 6. Funded Projects Starting from my Ph.D., I have actively cooperated to national-and european-funded scientific projects, Experimental modeling of ballistic applications via Finite State Machines ? Ana Agudo some cases I have contributed in the redaction of the project proposal, 2006.
, 720M?) Goal of the project: using GRAAL, the designer can define a dependable SRAM architecture, which achieves the target dependability requirements and design constraints. The dependable SRAM architecture is designed in order to guarantee high reliability levels. It includes the Built-In-Self-Test (BIST) logic for memory testing: it allows testing the memory using OFFline and/or ON-line testing strategies, the case of ON-line testing, the implementation of both Concurrent and Not- Concurrent test strategies is supported. Moreover, the dependable SRAM architecture can also include the Built-In Self Repair (BISR) logic for functional memory repairing
, Quality and Reliability of Complex Systems-on-Chip Place and period, Details Habilitation à Diriger les Recherches -Giorgio Di Natale 7. Cooperations 7.1. Universities, 2001.
, Politecnico di Torino): Paolo, Alfredo and Silvia have been my PhD supervisor Stefano (who made the PhD studies at the same time as me) shared many research topics with me, leading to several publications. The cooperation lasted also after moving to LIRMM, by keeping on developing techniques for the evaluation and the improvement of the reliability of a system
, Politecnico di Torino): we shared for 4 years (from 2009 to 2013) the coordination of the European section of the Test Technology Technical Council
, Sud): we shared for 4 years (from 2009 to 2013) the coordination of the working group " Security of Digital Embedded Systems " of the GDR SoC-SiP. Guy was the chair of the working group while I was the vice co-chair
, TIMA Lab): we presented together a tutorial titled, Test & Security " during the European Test Symposium, 2009.
, ): we cooperated to join our knowledge of test and repair of memories. The result of the cooperation has been two common papers
, ): in the context of the TReDiCo project, we developed a method for the built-in generation of test vectors for delay faults, 2004.
, Iran from 2006 to 2007): we developed a new approach for the soft error evaluation based on the use of the UML for the model of the target system
, Said is actively involved in the TRUDEVICE COST Action. Moreover, we are planning a common proposal for an Horizon 2020 project on security, 2012.
, from 2011): this collaboration started with the MASTER 3D project and the co-supervision of the PhD student Yassine Fkih. We published some common papers ([P34]
, Mentor Graphics, from 2013): together with Pascal Vivet we defined a novel test access method based on IJTAG for 3D circuits. We recently made a common presentation
, this cooperation lasts from many years. I worked with him on memory testing in the framework of the GRAAL project After that, we designed together a watchdog process to increase the reliability of Chapter II: Details Habilitation à Diriger les Recherches -Giorgio Di Natale 8. Dissemination of knowledge and scientific excellence 8.1. Executive and organizing committees TRUDEVICE Workshops: I organized as General Chair the first workshop for the COST Action TRUDEVICE on May 30-31, 2013 in Avignon (France) and the second on, in Paderborn (Germany). Both workshops are held in conjunction with the European Test Symposium European Test Symposium (ETS): I have been Publication Chair from 2012 and I will cover the role of Vice-Program Chair for ETS'15 in Cluj-Napoca (Romania), 2001.
, Rouzeyre On Countermeasures Against Fault Attacks on Advanced Encryption StandardFault Analysis in Cryptography", in the series "Springer-Verlag's Information Security and Cryptography, Reviewer for the following Journals: ? IEEE Transaction on Computer ? IEEE Flottes and B. Rouzeyre Fault Detection in Crypto-Devices, In book "Fault Detection, pp.2012-978, 2010.
, Ingrid Verbauwhede Test versus Security: Past and Present, IEEE Transactions on Emerging Topics in Computing, 2014.
, Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, Microelectronics Reliability, 1320.
, Bruno Rouzeyre Thwarting Scan-Based Attacks on Secure-ICs with On-Chip Comparison, IEEE Transaction on VLSI
, Rouzeyre A New Recovery Scheme against Short-to-Long Duration Transient Faults in Combinational Logic, Journal of Electronic Testing, pp.10-1007
, Bruno Rouzeyre A Novel Differential Scan Attack on Advanced DFT Structures, ACM Transactions on Design Automation of Electronic Systems, vol.18, issue.4 58, pp.10-1145, 2013.
, Scan attacks on side-channel and fault attack resistant public-key implementations, Journal of Cryptographic Engineering, vol.49, issue.9, pp.207-219, 2012.
DOI : 10.1007/s13389-012-0045-z
URL : https://hal.archives-ouvertes.fr/lirmm-01075412
, Statistical reliability estimation of microprocessor-based systems Rouzeyre Self-Test Techniques for Crypto-Devices, IEEE Transaction on VLSI Systems DOI: 10.1109/TVLSI, Test BDN: A new March Test for Dynamic Faults, Journal of Control Engineering and Applied Informatics (CEAI), Nr, pp.1-5, 2008.
, Art March Test for Realistic Static Linked Faults and Dynamic Faults in SRAMs, IEE Proceedings Computers and Digital Techniques Publications Habilitation à Diriger les Recherches -Giorgio Di Natale Programmable Built-In Self-Testing of Embedded RAM Clusters in System-on-Chip Architectures Prinetto, On-Line Self-Repair of Finite Impulse Response Filters, IEEE Design and Test of Computers, pp.237-245, 2003.
, An On-line BISTed RAM Architecture with Self Repair Capabilities Prinetto, On-line & Off-line BIST in IP-Core Design, IEEE Transaction on Reliability IEEE Design and Test of Computers, vol.51, issue.18 5, pp.128-92, 2001.
, Hakim Zimouche Built-In Self-Test for Manufacturing TSV Defects before bonding, IEEE VLSI Test Symposium, p.14, 2014.
, Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'13
DOI : 10.1016/j.microrel.2013.07.069
URL : https://hal.archives-ouvertes.fr/emse-01100723
, Juergen Schloeffel 3D Design For Test Architectures Based on IEEE P1687
, Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection, 24th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'13
DOI : 10.1016/j.microrel.2013.07.069
URL : https://hal.archives-ouvertes.fr/emse-01100723
, Bruno Rouzeyre A Single Built-in Sensor to Check Pull-up and Pull-down CMOS Networks against Transient Faults, 23th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS'13
, Marie-Lise Flottes and Bruno Rouzeyre Laser-Induced Fault Simulation, 16th Euromicro Conference on Digital System Design, 2013.
DOI : 10.1109/dsd.2013.72
, Rouzeyre A Smart Test Controller for Scan Chains in Secure Circuits, IEEE International On-Line Testing Symposium 2013 (IOLTS,13), 2013.
, Rouzeyre tLIFTING: an Open-Source Multi-Level Fault Simulator for Ionizing Effects, 9th Conference on Ph Di Natale A JTAG Based 3D DfT Architecture Using Automatic Die Detection, 9th Rouzeyre A multi-level simulation tool for laser attacks, Research in Microelectronics and Electronics -BRONZE LEAF Certificate Chapter IV: Publications Habilitation à Diriger les CryptArchi'13: Cryptographic Architectures Embedded in Reconfigurable Devices, France (2013) [P31] Giorgio Di Natale Manufacturing Test of 3D Stacked ICs: Problems, Solutions and Standards, Design for 3D Workshop, 2013.
, Bruno Rouzeyre A Bulk Built-in Sensor for Detection of Fault Attacks, IEEE International Symposium on HARDWARE-ORIENTED SECURITY and TRUST (HOST'13
, Rouzeyre Laser-Induced Fault Simulation, 1st TRUDEVICE Workshop
DOI : 10.1109/dsd.2013.72
, Rouzeyre Identification of Hardware Trojan's Triggering Signals, 1st TRUDEVICE Workshop: A COST Action on "Trustworthy Manufacturing and Utilization of Secure Devices, ETS'13), 2013.
, Rouzeyre tLIFTING: an Open-Source Delay-Annotated Fault Simulator, XXVII Conference on Design of Circuits and Integrated Systems, DCIS'2012), 2012.
, Rouzeyre Is Side-Channel Analysis really reliable for detecting Hardware Trojans, XXVII Conference on Design of Circuits and Integrated Systems (DCIS'2012), 2012.
, Rouzeyre On-chip test comparison for protecting confidential data in secure ICs, XXVII Conference on Design of Circuits and Integrated Systems (DCIS'2012), 2012.
, A New Scan Attack on RSA in Presence of Industrial Countermeasures, Lecture Notes in Computer Science, vol.7275, pp.89-104
DOI : 10.1007/978-3-642-29912-4_8
, Rouzeyre, I. Verbauwhede A New Scan Attack on Elliptic Curve Cryptosystems in presence of Industrial Design for Testability Structures, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'12
, Bruno Rouzeyre Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode, 23th European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF'12
, Rouzeyre On-chip test comparison for protecting confidential data in secure ICs, IEEE European Test Symposium, vol.2012, issue.12
, Rouzeyre Are advanced DfT structures sufficient for preventing scan-attacks, IEEE VLSI Test Symposium 2012 (VTS'12), pp.246-251
, Hernandez Exact Wafer Matching Process for 3D Wafer-to-Wafer Integration, 3D Integration: Applications, Technology, Architecture, Design, Automation, and Test Workshop
, Rouzeyre A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep- Submicron Technologies, IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp.3-5302, 2011.
, Rouzeyre How to Sample Results of Concurrent Error Detection Schemes in Transient Fault Scenarios?, RADECS'2011: Conference on Radiation Effects on Components and Systems, Chapter RADECS, issue.C11, pp.635-642, 2011.
, Rouzeyre New side-channel attack against scan chains, CryptArchi'11: Cryptographic Architectures Embedded in Reconfigurable Devices, 2011.
, Rouzeyre New security threats against chips containing scan chain structures, IEEE International Symposium on Hardware-Oriented Security and Trust, issue.11, pp.105-110, 2011.
, Rouzeyre Scan attacks and countermeasures in presence of scan response compactors, ETS'11), pp.19-24, 2011.
, Real Power Consumption Traces Realignment to Improve Differential Power Analysis, Diagnostics of Electronic Circuits and Systems (DDECS'11), 2010.
, Rouzeyre Timing issues for an efficient use of concurrent error detection codes, IEEE Latin American Test Workshop, issue.11, pp.1-6, 2011.
, Di Natale Parallel Test of Identical Cores using Test Elevators in 3D circuits extended abstract, IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST'10), 2010.
, Rouzeyre Evaluation of Concurrent error detection techniques on the Advanced Encryption Standard, Line Testing Symposium 2010 (IOLTS,10), pp.223-228, 2010.
, Rouzeyre Waveforms re-alignment to improve DPA attacks, CryptArchi'10: Cryptographic Architectures Embedded in Reconfigurable Devices, 2010.
, Rouzeyre Evaluation of Concurrent error detection techniques on the Advanced Encryption Standard, Presented to IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'10), pp.252-252, 2010.
, Rouzeyre Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers, IEEE International Symposium on Electronic Design Vietnam, pp.256-261, 2010.
, Bruno Rouzeyre An Integrated Validation Environment for Differential Power Analysis LIFTING: an Open-Source Logic Simulator, DATE 2010, Test and Security, 2010.
, Rouzeyre Execution Time Reduction of Differential Power Analysis Experiments, IEEE Latin American Test Workshop, 2009.
, Flottes Embedded Tutorial on "Test and Security, 2009.
, LIFTING: A Flexible Open-Source Fault Simulator, 2008 17th Asian Test Symposium, 2008.
DOI : 10.1109/ATS.2008.17
URL : https://hal.archives-ouvertes.fr/lirmm-00343610
, LIFTING: an Open-Source Logic Simulator, SAME (Sophia Antipolis Micro Electronics) Bruno Rouzeyre An Integrated Validation Environment for Differential Power Analysis, SAME (Sophia Antipolis Micro Electronics), Forum Forum, pp.49-56, 2008.
, Sybille Hellebrand A Modular Memory BIST for Optimized Memory Repair, IEEE International On-Line Testing Symposium, pp.171-172, 2008.
, An Integrated Validation Environment for Differential Power Analysis, CryptArchi'08: Cryptographic Architectures Embedded in Reconfigurable Devices Rouzeyre Stuck-at-Faults Test using Differential Power Analysis, France, 2008.
, March Test BDN: A new March Test for dynamic faults, 2008 IEEE International Conference on Automation, Quality and Testing, Robotics, pp.85-89, 2008.
DOI : 10.1109/AQTR.2008.4588712
URL : https://hal.archives-ouvertes.fr/lirmm-00303528
, Rouzeyre A Reliable Architecture for the Advanced Encryption Standard, IEEE European Test Symposium, pp.13-18, 2008.
, Rouzeyre Low-Cost Self-Test of Crypto Devices, Workshop on Dependable and Secure Nanocomputing, 2008.
, Rouzeyre Observability of Stuck-at-Faults with Differential Power Analysis, Puebla (Mexico), 2008.
, Rouzeyre An Integrated Validation Environment for Differential Power Analysis, IEEE International Symposium on Electronic Design, pp.527-532, 2008.
, Giorgio Di Natale Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC, IEEE International On-Line Testing Symposium, pp.205-206, 2007.
, Heraklion (Crete, Greece) Bruno Rouzeyre A Dependable Parallel Architecture for SBoxes, Reconfigurable Communication-Centric SoCs, Line Fault Detection Scheme for SBoxes in Secure CircuitsLine Testing Symposium Montpellier : France Edinburgh (UK) [P5] Flottes M CryptArchi'07: Cryptographic Architectures Embedded in Reconfigurable Devices, France (2007) Chapter IV: Publications Habilitation à Diriger les Recherches -Giorgio Di Natale [W10] Di Natale G., Flottes M.-L., Rouzeyre B. A Novel Parity Bit Scheme for SBOX in AES Circuits, IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'07), pp.57-62, 2007.
, Prinetto Memory Fault Simulator for Static-Linked Faults, Fukuoka (J), 2006.
, Prinetto ATPG For Dynamic Burn-In Test in Full-Scan Circuits, Natale A tool for teaching memory testing based on BIST, Baltic Electronics Conference, pp.1-4, 2006.
, Simlastik Interactive Educational Tool for Memory Testing, 6th European Workshop on Microelectronics Education, Stockholm (Sweden) Prinetto Single-Event Upset Analysis and Protection in High Speed Circuits, pp.29-34, 2006.
, Prinetto 22n March Test for Realistic Static Linked Faults in SRAMs, IEEE European Test Symposium, pp.49-54, 2006.
, Turcotti A board implementation for Fast APA Acoustic Echo Canceller using ADSP-21065L DSP Robotics (AQTR'06) Prinetto Automatic March Tests Generations for Static Linked Faults in SRAMs, IEEE International Conference on Automation, Quality & Testing Munich (D), pp.1-6, 2006.
, Prinetto A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs, Diagnostics of Electronic Circuits and Systems (DDECS'06), pp.155-156, 2006.
, Prinetto Automatic March Tests Generation for Multi-Port SRAMs New March Tests for Unlinked Dynamic Memory Faults Built-in Self-Test Generation for Delay Faults -a case study, 5th Electronic Circuits and Systems Conference (ECS'05), 2005.
, Automatic March Tests Generation for Static and Dynamic Faults in SRAMs, European Test Symposium (ETS'05), pp.122-127, 2005.
DOI : 10.1109/ETS.2005.8
, PROMON: A Profile Monitor of Software Applications, 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05), pp.81-86, 2005.
, AFSM-Based Deterministic Hardware TPG, 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS'05) Exhaustive test of several dependable memory architectures designed by GRAAL tool, IEEE 12th Asian Test Symposium, pp.178-181, 2003.
, Data criticality estimation in software applications, International Test Conference, 2003. Proceedings. ITC 2003., pp.802-810, 2003.
DOI : 10.1109/TEST.2003.1270912
, FAUST: fault-injection script-based tool, 9th IEEE On-Line Testing Symposium, 2003. IOLTS 2003., p.160, 2003.
DOI : 10.1109/OLT.2003.1214386
, Data Criticality Estimation in Software Applications Specification and Design of a new Memory Fault Simulator, IEEE European IEEE Asian Test Symposium, pp.231-236, 2002.
, Static Analysis of SEU Effects on Software Applications An Optimal Algorithm for the Automatic Generation of March Tests, IEEE Design Automation and Test Conference in Europe Memory Read Faults: Taxonomy and Automatic Test Generation, Control-Flow Checking Via Regular Expressions Kyoto (J) Kyoto (J) GRAAL: a Tool for Highly Dependable SRAMs Generation, IEEE International Test Conference (ITC01), pp.500-508, 2001.
, Software dependability techniques validated via fault injection experiments, RADECS 2001. 2001 6th European Conference on Radiation and Its Effects on Components and Systems (Cat. No.01TH8605), pp.269-274, 2001.
DOI : 10.1109/RADECS.2001.1159292
, Validation of a software dependability tool via fault injection experiments, Proceedings Seventh International On-Line Testing Workshop, pp.3-8, 2001.
DOI : 10.1109/OLT.2001.937809
, SEU Effect Analysis in Open-Source Router via a Distributed Fault Injection Environment On Evaluating DSP-based Architectures for Space Application, Munich (D) XV Conference on Design of Circuits and Integrated Systems (DCIS'2000) Prinetto, A programmable BIST architecture for clusters of Multiple-Port SRAMs, IEEE International Test Conference (ITC00), Atlantic City (NJ), pp.219-223, 2000.
, A family of Self-Repair SRAM cores, International On-Line Test Workshop, Majorca (ES), pp.214-218, 2000.
, An effective distributed BIST architecture for RAMs, Lisbon (P), pp.119-124, 2000.
, Rouzeyre A New Recovery Scheme against Short-to-Long Duration Transient Faults in Combinational Logic, Journal of Electronic Testing, pp.10-1007
, Di Natale Statistical reliability estimation of microprocessor-based systems DOI: 10.1109/TC Rouzeyre Self-Test Techniques for Crypto-Devices, IEEE Transaction on VLSI Systems, IEEE Transaction on Computer Test Generation Revealed IEEE Transaction on Computer, vol.99, issue.12s, pp.188-197, 1109.