Random Adjacent Sequences, pp.413-424 ,
DOI : 10.1007/978-0-387-35597-9_35
URL : https://hal.archives-ouvertes.fr/lirmm-00268500
Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles, Landrault VLSI-Soc: From Systems to Silicon, pp.267-281 ,
DOI : 10.1007/978-0-387-73661-7_17
URL : https://hal.archives-ouvertes.fr/lirmm-00194261
A Scan-BIST Structure to Test Delay Faults in Sequential Circuits, Virazel Journal of Electronic Testing Theory and Applications, vol.14, issue.12, pp.95-102 ,
Delay fault testing: choosing between random SIC and random MIC test sequences, Proceedings IEEE European Test Workshop, pp.233-241 ,
DOI : 10.1109/ETW.2000.873772
URL : https://hal.archives-ouvertes.fr/lirmm-00345796
On hardware generation of random single input change test sequences, IEEE European Test Workshop, 2001., pp.145-157 ,
DOI : 10.1109/ETW.2001.946674
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test, Journal of Electronic Testing, vol.14, issue.2, pp.169-179 ,
DOI : 10.1007/s10836-005-6146-1
URL : https://hal.archives-ouvertes.fr/lirmm-00105313
Efficient March Test Procedure for Dynamic Read Destructive Fault Detection in SRAM Memories, Journal of Electronic Testing, vol.21, issue.5, pp.551-561 ,
DOI : 10.1007/s10836-005-1169-1
URL : https://hal.archives-ouvertes.fr/lirmm-00105314
A Gated Clock Scheme for Low Power Testing of Logic Cores, Journal of Electronic Testing, vol.23, issue.7, pp.89-99 ,
DOI : 10.1007/s10836-006-6259-1
URL : https://hal.archives-ouvertes.fr/lirmm-00134766
ADOFs and Resistive-ADOFs in SRAM Address Decoders: Test Conditions and March Solutions, Journal of Electronic Testing, vol.14, issue.2, pp.287-296 ,
DOI : 10.1007/s10836-006-7761-1
URL : https://hal.archives-ouvertes.fr/lirmm-00134769
Analysis and Test of Resistive-Open Defects in SRAM Pre-Charge Circuits, Journal of Electronic Testing, vol.19, issue.5, pp.435-444 ,
DOI : 10.1007/s10836-007-5003-9
URL : https://hal.archives-ouvertes.fr/lirmm-00194254
A Selective Scan Slice Encoding Technique for Test Data Volume and Test Power Reduction, Journal of Electronic Testing, vol.1, issue.3, pp.353-364 ,
DOI : 10.1007/s10836-007-5053-z
URL : https://hal.archives-ouvertes.fr/lirmm-00331296
New March Elements for Address Decoder Open and Resistive Open Fault Detection in SRAM Memories, Journal of Integrated Circuits and Systems, vol.3, issue.1, pp.7-12 ,
URL : https://hal.archives-ouvertes.fr/lirmm-00341793
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash, Journal of Electronic Testing, vol.3, issue.2-3, pp.127-144 ,
DOI : 10.1007/s10836-008-5096-9
Analysis of Resistive-Open Defects in SRAM Sense Amplifiers, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, issue.10, pp.1556-1158 ,
DOI : 10.1109/TVLSI.2008.2005194
URL : https://hal.archives-ouvertes.fr/lirmm-00371367
Is TMR Suitable for Yield Improvement, Virazel IET Computers and Digital Techniques, pp.581-592 ,
DOI : 10.1049/iet-cdt.2008.0127
URL : https://hal.archives-ouvertes.fr/lirmm-00406961
A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects, IEEE Transactions on Computers, vol.59, issue.3, pp.289-300 ,
DOI : 10.1109/TC.2009.177
URL : https://hal.archives-ouvertes.fr/lirmm-00553545
A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for, Ahmed Journal of Low Power Electronics, vol.6, issue.2, pp.359-374 ,
SoC yield Improvement -Using TMR Architectures for Manufacturing Defect Tolerance in Logic Cores, Pravossoudovitch International Journal on Advances in Systems and Measurements, vol.3, issue.1&2, pp.1-10, 1942. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00553567
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL eFlash Memories, Journal of Electronic Testing, vol.85, issue.8, pp.215-228 ,
DOI : 10.1007/s10836-012-5277-4
Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes, Journal of Electronic Testing, vol.5, issue.4, pp.317-329 ,
DOI : 10.1007/s10836-012-5291-6
URL : https://hal.archives-ouvertes.fr/lirmm-00805017
Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation, Virazel IEEE Transactions on VLSI Systems ,
DOI : 10.1109/TVLSI.2012.2197427
URL : https://hal.archives-ouvertes.fr/lirmm-00806774
A Study of Tapered 3-D TSVs for Power and Thermal Integrity, Dilillo, A. Virazel IEEE Transactions on VLSI Systems, pp.306-319 ,
DOI : 10.1109/TVLSI.2012.2187081
URL : https://hal.archives-ouvertes.fr/lirmm-00806776
Testing a Commercial MRAM Under Neutron and Alpha Radiation in Dynamic Mode, IEEE Transactions on Nuclear Science, vol.60, issue.4, pp.1-6 ,
DOI : 10.1109/TNS.2013.2239311
URL : https://hal.archives-ouvertes.fr/lirmm-00805005
Globally Constrained Locally Optimized 3D Power Delivery Networks, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01255754
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.11, 2013. ,
DOI : 10.1109/TVLSI.2013.2294080
URL : https://hal.archives-ouvertes.fr/lirmm-01248578
Evaluating a radiation monitor for mixed-field environments based on SRAM technology, Journal of Instrumentation, vol.9, issue.05, pp.1748-022105, 1088. ,
DOI : 10.1088/1748-0221/9/05/C05052
URL : https://hal.archives-ouvertes.fr/lirmm-01234448
A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems, Journal of Electronic Testing, vol.3, issue.6, 1007. ,
DOI : 10.1007/s10836-014-5459-3
URL : https://hal.archives-ouvertes.fr/lirmm-01272958
An SRAM Based Monitor for Mixed-Field Radiation Environments, IEEE Transactions on Nuclear Science, vol.61, issue.4, 2014. ,
DOI : 10.1109/TNS.2014.2299733
URL : https://hal.archives-ouvertes.fr/lirmm-01234441
Multiple Cell Upset Classification<newline/> in Commercial SRAMs, IEEE Transactions on Nuclear Science, vol.61, issue.4, 2014. ,
DOI : 10.1109/TNS.2014.2313742
A new Scan-BIST structures to test delay faults in sequential circuits, pp.27-29, 1998. ,
A BIST structure to test delay faults in a scan environment, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259), pp.25-27, 1998. ,
DOI : 10.1109/ATS.1998.741653
URL : https://hal.archives-ouvertes.fr/lirmm-00345798
Delay fault testing: choosing between random SIC and random MIC test sequences, Proceedings IEEE European Test Workshop, pp.23-26, 2000. ,
DOI : 10.1109/ETW.2000.873772
URL : https://hal.archives-ouvertes.fr/lirmm-00345796
On hardware generation of random single input change test sequences, IEEE European Test Workshop, 2001., pp.29-30, 2001. ,
DOI : 10.1109/ETW.2001.946674
Defect-Oriented Dynamic Fault Models for Embedded SRAMs The Netherlands, 25-28 mai, pp.23-27, 2003. ,
Comparison of open and resistive-open defect test conditions in SRAM address decoders, Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-03, pp.17-19, 2003. ,
DOI : 10.1109/ATS.2003.1250818
URL : https://hal.archives-ouvertes.fr/lirmm-01238821
Design of Routing-Constrained Low Power Scan Chains, Electronic Design, Test and Applications, pp.28-30, 2004. ,
DOI : 10.1109/date.2004.1268828
URL : https://hal.archives-ouvertes.fr/lirmm-00108833
Design of Routing-Constrained Low Power Scan Chains, Pravossoudovitch, A. Virazel DATE'2004 : Design Automation and Test in Europe, pp.16-20, 2004. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00108833
March Tests Improvements for Address Decoder Open and Resistive Open Fault Detection, pp.8-10, 2004. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00108642
March iC-: An Improved Version of March C- for ADOFs Detection, 22nd IEEE VLSI Test Symposium, 2004. Proceedings., pp.25-29, 2004. ,
DOI : 10.1109/VTEST.2004.1299236
URL : https://hal.archives-ouvertes.fr/lirmm-00108772
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., pp.23-26, 2004. ,
DOI : 10.1109/ETSYM.2004.1347645
Efficient Test of Dynamic Read Destructive Faults in SRAM Memories, pp.30-32, 2005. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00106515
Peak Power Consumption during Scan Testing: Issue, Analysis and Heuristic Solution, Virazel DDECS'2005 : Design and Diagnostics of Electronic Circuits and Systems, pp.13-16, 2005. ,
DOI : 10.1109/dtis.2006.1708693
URL : https://hal.archives-ouvertes.fr/lirmm-00105990
Data Retention Fault in SRAM Memories: Analysis and Detection Procedures, 23rd IEEE VLSI Test Symposium (VTS'05), pp.1-5, 2005. ,
DOI : 10.1109/VTS.2005.37
URL : https://hal.archives-ouvertes.fr/lirmm-00105995
Resistive-Open Defect Influence in SRAM Pre-Charge Circuits: Analysis and Characterization, European Test Symposium (ETS'05), pp.22-25, 2005. ,
DOI : 10.1109/ETS.2005.33
URL : https://hal.archives-ouvertes.fr/lirmm-00106010
Resistive-open defect injection in SRAM core-cell, Proceedings of the 42nd annual conference on Design automation , DAC '05, pp.13-17, 2005. ,
DOI : 10.1145/1065579.1065804
URL : https://hal.archives-ouvertes.fr/lirmm-00136906
Why Do We Need to Reduce Peak Power Consumption During Scan Capture, Landrault PATMOS'2005 : International workshop on Power and Timing Modeling, Optimization and Simulation, pp.20-23, 2005. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00106111
Power-Aware Scan Testing for Peak Power Reduction, Landrault VLSI-SOC'2005 : IFIP International Conference on Very Large Scale Integration, pp.17-19, 2005. ,
DOI : 10.1109/vlsisoc.2006.313222
URL : https://hal.archives-ouvertes.fr/lirmm-00106112
March Pre: an Efficient Test for Resistive-Open Defects in the SRAM Pre-charge Circuit, 2006 IEEE Design and Diagnostics of Electronic Circuits and systems, 2006. ,
DOI : 10.1109/DDECS.2006.1649631
URL : https://hal.archives-ouvertes.fr/lirmm-00134776
An Overview of Failure Mechanisms in Embedded Flash Memories, 24th IEEE VLSI Test Symposium, pp.30-34, 2006. ,
DOI : 10.1109/VTS.2006.19
URL : https://hal.archives-ouvertes.fr/lirmm-00102761
Minimizing Peak Power Consumption during Scan Testing: Structural Technique for Don't Care Bits Assignment, 2006 Ph.D. Research in Microelectronics and Electronics, pp.12-15, 2006. ,
DOI : 10.1109/RME.2006.1689897
URL : https://hal.archives-ouvertes.fr/lirmm-00137614
Minimizing peak power consumption during scan testing: test pattern modification with X filling heuristics, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., pp.5-7, 2006. ,
DOI : 10.1109/DTIS.2006.1708693
URL : https://hal.archives-ouvertes.fr/lirmm-00093690
Embedded flash testing: overview and perspectives, International Conference on Design and Test of Integrated Systems in Nanoscale Technology, 2006. DTIS 2006., pp.5-7, 2006. ,
DOI : 10.1109/DTIS.2006.1708721
URL : https://hal.archives-ouvertes.fr/lirmm-00093665
Unified Framework for Logic Diagnostic, pp.15-19, 2006. ,
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing, 2006 IFIP International Conference on Very Large Scale Integration, pp.16-18, 2006. ,
DOI : 10.1109/VLSISOC.2006.313222
URL : https://hal.archives-ouvertes.fr/lirmm-00108141
Power-Aware Test Data Compression for Embedded IP Cores, 2006 15th Asian Test Symposium, pp.15-17, 2006. ,
DOI : 10.1109/ATS.2006.260985
A Mixed Approach for Unified Logic Diagnosis Virazel DDECS'2007 : Design and Diagnostics of Electronic Circuits and Systems, pp.11-13, 2006. ,
Slow Write Driver Faults in 65nm SRAM Technology: Analysis and March Test Solution, Pravossoudovitch, A. Virazel, M. Bastian DATE'2007 :, Design Automation and Test in Europe, pp.239-242, 2007. ,
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window, 25th IEEE VLSI Test Symmposium (VTS'07), pp.6-10, 2007. ,
DOI : 10.1109/VTS.2007.52
URL : https://hal.archives-ouvertes.fr/lirmm-00151034
Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs, 25th IEEE VLSI Test Symmposium (VTS'07), pp.6-10, 2007. ,
DOI : 10.1109/VTS.2007.84
URL : https://hal.archives-ouvertes.fr/lirmm-00155979
Electrical Simulation Model of the 2T-FLOTOX Core-Cell for Defect Injection and Faulty Behavior Prediction in eFlash Memories, 12th IEEE European Test Symposium (ETS'07), pp.20-24, 2007. ,
DOI : 10.1109/ETS.2007.20
URL : https://hal.archives-ouvertes.fr/lirmm-00158543
Dynamic Two-Cell Incorrect Read Fault Due to Resistive-Open Defects in the Sense Amplifiers of SRAMs, 12th IEEE European Test Symposium (ETS'07), pp.20-24, 2007. ,
DOI : 10.1109/ETS.2007.19
URL : https://hal.archives-ouvertes.fr/lirmm-00158116
DERRIC: A Tool for Unified Logic Diagnosis, 12th IEEE European Test Symposium (ETS'07), pp.20-24, 2007. ,
DOI : 10.1109/ETS.2007.16
URL : https://hal.archives-ouvertes.fr/lirmm-00155993
Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior, 16th Asian Test Symposium (ATS 2007), pp.9-11, 2007. ,
DOI : 10.1109/ATS.2007.121
URL : https://hal.archives-ouvertes.fr/lirmm-00179276
Fast Bridging Fault Diagnosis using Logic Information, 16th Asian Test Symposium (ATS 2007), pp.9-11, 2007. ,
DOI : 10.1109/ATS.2007.75
URL : https://hal.archives-ouvertes.fr/lirmm-00179259
A concurrent approach for testing address decoder faults in eFlash memories, 2007 IEEE International Test Conference, pp.23-25, 2007. ,
DOI : 10.1109/TEST.2007.4437567
URL : https://hal.archives-ouvertes.fr/lirmm-00194260
Improving Diagnosis Resolution without Physical Information, 4th IEEE International Symposium on Electronic Design, Test and Applications (delta 2008), 2008. ,
DOI : 10.1109/DELTA.2008.37
A Design-for-Diagnosis Technique for SRAM Write Drivers, Design Automation and Test in Europe, 2008. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00341796
A signature-based approach for diagnosis of dynamic faults in SRAMs, 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era, pp.25-28, 2008. ,
DOI : 10.1109/DTIS.2008.4540243
URL : https://hal.archives-ouvertes.fr/lirmm-00324143
An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing, 26th IEEE VLSI Test Symposium (vts 2008), pp.4-8, 2008. ,
DOI : 10.1109/VTS.2008.17
URL : https://hal.archives-ouvertes.fr/lirmm-00281558
Yield Improvement, Fault-Tolerance to the Rescue?, 2008 14th IEEE International On-Line Testing Symposium, 2008. ,
DOI : 10.1109/IOLTS.2008.10
URL : https://hal.archives-ouvertes.fr/lirmm-00303400
Using TMR Architectures for Yield Improvement, 2008 IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems, pp.1-3, 2008. ,
DOI : 10.1109/DFT.2008.23
URL : https://hal.archives-ouvertes.fr/lirmm-00406967
A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs, 2008 IEEE International Test Conference, pp.28-30, 2008. ,
DOI : 10.1109/TEST.2008.4700555
URL : https://hal.archives-ouvertes.fr/lirmm-00341798
SoC Yield Improvement: Redundant Architectures to the Rescue?, 2008 IEEE International Test Conference, pp.28-30, 2008. ,
DOI : 10.1109/TEST.2008.4700686
URL : https://hal.archives-ouvertes.fr/lirmm-00341799
A new design-for-test technique for SRAM core-cell stability faults, 2009 Design, Automation & Test in Europe Conference & Exhibition, pp.20-24, 2009. ,
DOI : 10.1109/DATE.2009.5090873
URL : https://hal.archives-ouvertes.fr/lirmm-00371374
A case study on logic diagnosis for System-on-Chip, 2009 10th International Symposium on Quality of Electronic Design, pp.16-18, 2009. ,
DOI : 10.1109/ISQED.2009.4810303
URL : https://hal.archives-ouvertes.fr/lirmm-00370646
Comprehensive bridging fault diagnosis based on the SLAT paradigm, 2009 12th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.15-17, 2009. ,
DOI : 10.1109/DDECS.2009.5012142
URL : https://hal.archives-ouvertes.fr/lirmm-00371198
A fault-simulation-based approach for logic diagnosis, 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era, pp.6-9, 2009. ,
DOI : 10.1109/DTIS.2009.4938058
URL : https://hal.archives-ouvertes.fr/lirmm-00371377
Using TMR Architectures for SoC yield, The First International Conference on Advances in System Testing and Validation Lifecycle, pp.20-25, 2009. ,
DOI : 10.1109/valid.2009.26
URL : https://hal.archives-ouvertes.fr/lirmm-00406967
NAND flash testing: A preliminary study on actual defects, 2009 International Test Conference, pp.1-6, 2009. ,
DOI : 10.1109/TEST.2009.5355898
URL : https://hal.archives-ouvertes.fr/lirmm-00433765
Delay Fault Diagnosis in Sequential Circuits, 2009 Asian Test Symposium, pp.23-26, 2009. ,
DOI : 10.1109/ATS.2009.16
URL : https://hal.archives-ouvertes.fr/lirmm-00406968
Impact of Resistive-Bridging Defects in SRAM Core-Cell, 2010 Fifth IEEE International Symposium on Electronic Design, Test & Applications, pp.13-15, 2010. ,
DOI : 10.1109/DELTA.2010.31
URL : https://hal.archives-ouvertes.fr/lirmm-00553592
Detecting NBTI induced failures in SRAM core-cells, 2010 28th VLSI Test Symposium (VTS), 2010. ,
DOI : 10.1109/VTS.2010.5469612
URL : https://hal.archives-ouvertes.fr/lirmm-00553612
A Two-Layer SPICE Model of the ATMEL TSTACTM eFlash Memory Technology for Defect Injection and Faulty Behavior Prediction, pp.25-28, 2010. ,
Setting test conditions for improving SRAM reliability, 2010 15th IEEE European Test Symposium, pp.25-28, 2010. ,
DOI : 10.1109/ETSYM.2010.5512734
URL : https://hal.archives-ouvertes.fr/lirmm-00492741
Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes, 2010 15th IEEE European Test Symposium, pp.25-28, 2010. ,
DOI : 10.1109/ETSYM.2010.5512768
URL : https://hal.archives-ouvertes.fr/lirmm-00493236
A statistical simulation method for reliability analysis of SRAM core-cells, Proceedings of the 47th Design Automation Conference on, DAC '10, pp.13-18, 2010. ,
DOI : 10.1145/1837274.1837487
URL : https://hal.archives-ouvertes.fr/lirmm-00553619
Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes, 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.14-16, 2010. ,
DOI : 10.1109/DDECS.2010.5491748
Parity prediction synthesis for nano-electronic gate designs, 2010 IEEE International Test Conference, pp.1-5, 2010. ,
DOI : 10.1109/TEST.2010.5699312
URL : https://hal.archives-ouvertes.fr/lirmm-00537938
Is test power reduction through X-filling good enough?, 2010 IEEE International Test Conference, pp.1-5, 2010. ,
DOI : 10.1109/TEST.2010.5699297
URL : https://hal.archives-ouvertes.fr/lirmm-00537926
A Memory Fault Simulator for Radiation-Induced Effects in SRAMs, 2010 19th IEEE Asian Test Symposium, pp.2-4, 2010. ,
DOI : 10.1109/ATS.2010.26
URL : https://hal.archives-ouvertes.fr/lirmm-00545102
A Test Solution for Oxide Thickness Variations in the ATMEL T STAC eFlash Technology, Vachez DTIS'2011 : International Conference on Design & Test of Integrated Systems in Nanoscale Technology, pp.6-8, 2011. ,
Power Reduction Through X-filling of Transition Fault Test Vectors for, Ahmed DTIS'2011 : International Conference on Design & Test of Integrated Systems in Nanoscale Technology, pp.6-8, 2011. ,
On Using a SPICE-Like TSTACtm eFlash Model for Design, Vachez DDECS'2011 : Symposium on Design and Diagnostics of Electronic Systems, pp.13-15, 2011. ,
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.13-15, 2011. ,
DOI : 10.1109/DDECS.2011.5783110
URL : https://hal.archives-ouvertes.fr/lirmm-00679522
A study of path delay variations in the presence of uncorrelated power and ground supply noise, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.13-15, 2011. ,
DOI : 10.1109/DDECS.2011.5783078
URL : https://hal.archives-ouvertes.fr/lirmm-00592000
Power supply noise and ground bounce aware pattern generation for delay testing, 2011 IEEE 9th International New Circuits and systems conference, pp.26-29, 2011. ,
DOI : 10.1109/NEWCAS.2011.5981222
URL : https://hal.archives-ouvertes.fr/lirmm-00647815
On using address scrambling to implement defect tolerance in SRAMs, 2011 IEEE International Test Conference, pp.20-22, 2011. ,
DOI : 10.1109/TEST.2011.6139149
URL : https://hal.archives-ouvertes.fr/lirmm-00647773
Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector, 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, pp.3-5, 2011. ,
DOI : 10.1109/DFT.2011.41
URL : https://hal.archives-ouvertes.fr/lirmm-00651226
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits, 2011 Asian Test Symposium, pp.20-23, 2011. ,
DOI : 10.1109/ATS.2011.89
URL : https://hal.archives-ouvertes.fr/lirmm-00679513
Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling, 2011 Asian Test Symposium, pp.20-23, 2011. ,
DOI : 10.1109/ATS.2011.35
URL : https://hal.archives-ouvertes.fr/lirmm-00651247
Impact of Resistive-Open Defects on the Heat Current of, DATE'2012 : Design Automation and Test in Europe, pp.12-16, 2012. ,
A pseudo-dynamic comparator for error detection in fault tolerant architectures, 2012 IEEE 30th VLSI Test Symposium (VTS), pp.23-26, 2012. ,
DOI : 10.1109/VTS.2012.6231079
URL : https://hal.archives-ouvertes.fr/lirmm-00806778
Defect analysis in power mode control logic of low-power SRAMs, 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.28-29, 2012. ,
DOI : 10.1109/ETS.2012.6233033
URL : https://hal.archives-ouvertes.fr/lirmm-00805374
Through-Silicon-Via resistive-open defect analysis, 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.28-29, 2012. ,
DOI : 10.1109/ETS.2012.6233037
URL : https://hal.archives-ouvertes.fr/lirmm-00806848
Evaluation of test algorithms stress effect on SRAMs under neutron radiation, 2012 IEEE 18th International On-Line Testing Symposium (IOLTS), pp.27-29, 2012. ,
DOI : 10.1109/IOLTS.2012.6313853
URL : https://hal.archives-ouvertes.fr/lirmm-00805373
SRAM Core-Cell Sensitivity to Neutron at 40nm Technology Node, Saigné RADECS'2012 : European Conference on Radiation and its Effects on Components and Systems, pp.24-28, 2012. ,
Low-power SRAMs power mode control logic: Failure analysis and test solutions, 2012 IEEE International Test Conference, pp.4-9, 2012. ,
DOI : 10.1109/TEST.2012.6401578
URL : https://hal.archives-ouvertes.fr/lirmm-00805143
Through-Silicon-Via resistive-open defect analysis, 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.28-30, 2012. ,
DOI : 10.1109/ETS.2012.6233037
URL : https://hal.archives-ouvertes.fr/lirmm-00806848
Fault Localization Improvement through an Intra-Cell Diagnosis Approach, Auvray ISTFA'2012 : International Symposium for Testing and Failure Analysis, pp.15-26, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806863
Impact of Resistive-Bridge Defects in, Mackay ATS'2012 : Asian Test Symposium, 2012. ,
Power Supply Noise Sensor Based on Timing Uncertainty Measurements, 2012 IEEE 21st Asian Test Symposium, 2012. ,
DOI : 10.1109/ATS.2012.46
URL : https://hal.archives-ouvertes.fr/lirmm-00806890
Effect-Cause Intra-Cell Diagnosis at Transistor Level, Auvray ISQED'2013 : 14th International Symposium & Exhibits on Quality Electronic Desgn, USA, pp.4-6, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00817224
Test Solution for Data Retention Faults in Low-Power SRAMs, Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, pp.18-22, 2013. ,
DOI : 10.7873/DATE.2013.099
URL : https://hal.archives-ouvertes.fr/lirmm-00805140
Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures, 2013 8th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp.26-28, 2013. ,
DOI : 10.1109/DTIS.2013.6527775
URL : https://hal.archives-ouvertes.fr/lirmm-01248603
Fast and accurate electro-thermal analysis of three-dimensional power delivery networks, 2013 14th International Conference on Thermal, Mechanical and Multi-Physics Simulation and Experiments in Microelectronics and Microsystems (EuroSimE), pp.14-17, 2013. ,
DOI : 10.1109/EuroSimE.2013.6529956
URL : https://hal.archives-ouvertes.fr/lirmm-00839043
A built-in scheme for testing and repairing voltage regulators of low-power srams, 2013 IEEE 31st VLSI Test Symposium (VTS), pp.29-30 ,
DOI : 10.1109/VTS.2013.6548894
URL : https://hal.archives-ouvertes.fr/lirmm-00805366
Computing detection probability of delay defects in signal line tsvs, 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.27-31, 2013. ,
DOI : 10.1109/ETS.2013.6569349
URL : https://hal.archives-ouvertes.fr/lirmm-00839044
Analyzing resistive-open defects in SRAM core-cell under the effect of process variability, 2013 18TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.27-31, 2013. ,
DOI : 10.1109/ETS.2013.6569373
URL : https://hal.archives-ouvertes.fr/lirmm-00805360
Characterization of an SRAM based particle detector for mixed-field radiation environments, 5th IEEE International Workshop on Advances in Sensors and Interfaces IWASI, pp.13-14, 2013. ,
DOI : 10.1109/IWASI.2013.6576070
URL : https://hal.archives-ouvertes.fr/lirmm-00839046
Temperature Impact on the Neutron SER of a Commercial 90nm, Saigné NSREC'2013 : Nuclear and Space Radiation Effects Conference, pp.8-12, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00805291
SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations, 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), pp.8-10, 2013. ,
DOI : 10.1109/IOLTS.2013.6604066
URL : https://hal.archives-ouvertes.fr/lirmm-00818955
Mitigate TSV Electromigration for 3D ICs -From the Architecture Perspective, Belleville ISVLSI'2013 : International Symposium on VLSI, pp.5-7, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00839052
On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs, 2013 IEEE International Test Conference (ITC), pp.9-13, 2013. ,
DOI : 10.1109/TEST.2013.6651927
URL : https://hal.archives-ouvertes.fr/lirmm-00818977
Multiple-Cell-Upsets on a commercial 90nm SRAM in dynamic mode, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), pp.23-27, 2013. ,
DOI : 10.1109/RADECS.2013.6937429
URL : https://hal.archives-ouvertes.fr/lirmm-00839062
SEU monitoring in mixed-field radiation environments of particle accelerators, 2013 14th European Conference on Radiation and Its Effects on Components and Systems (RADECS), pp.23-27, 2013. ,
DOI : 10.1109/RADECS.2013.6937419
URL : https://hal.archives-ouvertes.fr/lirmm-00839085
On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell, 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), pp.2-4, 2013. ,
DOI : 10.1109/DFT.2013.6653597
URL : https://hal.archives-ouvertes.fr/lirmm-01238413
Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing, 2013 22nd Asian Test Symposium, pp.18-21, 2013. ,
DOI : 10.1109/ATS.2013.30
URL : https://hal.archives-ouvertes.fr/lirmm-01248609
Evaluating An SEU Monitor For Mixed-Field Radiation Environments, Saigné, International Workshop on Radiation Imagining Detector, 2013. ,
DOI : 10.1109/tns.2014.2299733
URL : https://hal.archives-ouvertes.fr/lirmm-01238433
TSV aware timing analysis and diagnosis in paths with multiple TSVs, 2014 IEEE 32nd VLSI Test Symposium (VTS), pp.13-17, 2014. ,
DOI : 10.1109/VTS.2014.6818772
URL : https://hal.archives-ouvertes.fr/lirmm-01248594
Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.23-25, 2014. ,
DOI : 10.1109/DDECS.2014.6868794
URL : https://hal.archives-ouvertes.fr/lirmm-01248598
Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.23-25, 2014. ,
DOI : 10.1109/DDECS.2014.6868791
URL : https://hal.archives-ouvertes.fr/lirmm-01248599
Timing-aware ATPG for critical paths with multiple TSVs, 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, pp.23-25, 2014. ,
DOI : 10.1109/DDECS.2014.6868774
URL : https://hal.archives-ouvertes.fr/lirmm-01248600
An Intra-Cell Defect Grading Tool, Virazel DDECS'2014 : Symposium on Design and Diagnostics of Electronic Systems, pp.23-25, 2014. ,
URL : https://hal.archives-ouvertes.fr/lirmm-01248591
A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise, 2014 IEEE Computer Society Annual Symposium on VLSI, pp.9-11, 2014. ,
DOI : 10.1109/ISVLSI.2014.42
URL : https://hal.archives-ouvertes.fr/lirmm-01248592
Efficient Dynamic Test Methods for COTS SRAMs Under Heavy Ion Irradiation, IEEE Nuclear and Space Radiation Effects Conferencee, 2014. ,
DOI : 10.1109/tns.2014.2363123
URL : https://hal.archives-ouvertes.fr/lirmm-01237660
Wrobel and F.Saigne IEEE Nuclear and Space Radiation Effects ConferenceeDynamic Fault in SRAM: Analysis and Test Approaches, Time Testing of 90nm COTS SRAMs at Concordia Station in Antarctica mai 2005 [CI2] "Low Power Testing" P. Girard, C. Landrault, S. Pravossoudovitch, A. Virazel WRTLT'06: 7th Workshop on RTL and High Level Testing, pp.22-25, 2006. ,
Impact of Technology Scaling on Defects and Parameter Deviations in Embedded SRAMs, pp.4-8, 2008. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00324151
Failure Analysis and Test Solutions for Low-Power SRAMs, Badereddine ATS'2011 : Asian Test Symposium Special Session on "Memory BIST Advances for Nanoscale Technologies, pp.506-510, 2011. ,
Advanced Test Methods for SRAMs, Pravossoudovitch, A. Virazel VTS'2012 : VLSI Test Symposium, Embedded Tutorial, pp.459-460, 2012. ,
An Introduction to Why and How Controlling Power Consumption During Test Todri et A. Virazel ATS'2012 : Asian Test Symposium, Special Session on " Power-Aware Testing: Present and Future, pp.300-301, 2012. ,
Analyse des capacités de test de générateurs intégrés produisant des vecteurs adjacents, Pravossoudovitch Colloque CAO de Circuits Intégrés et Systèmes, pp.10-12, 1999. ,
BIST Structures Generating Universal Test Sequences for Delay, Bridging and Stuck-at Faults" A, 2000. ,
Test Intégré de Circuits Digitaux : Etude Comparative de l'Efficacité de deux types de Séquences de Test, Pravossoudovitch JNRDM'2000: Journées Nationales du Réseau Doctoral de Microélectronique, pp.4-5, 2000. ,
Universal Test Sequences: A BIST Application, pp.21-23, 2001. ,
Test Intégré de Circuits Digitaux : Comparaison de deux types de Séquences de Test, pp.6-8, 2001. ,
Power Conscious BIST Approaches, pp.18-19, 2002. ,
Test of Delay Faults in SRAM Memories, pp.17-21, 2003. ,
Low Power Test Pattern Generation Technique for BIST with High Defect Coverage, pp.24-25, 2003. ,
Test of Dynamic Faults in SRAM Memories, South European Test Seminar, pp.15-19, 2004. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00106515
Low Power Testing for SOC Cores, South European Test Seminar, pp.15-19, 2004. ,
Test March pour la Détection des Fautes Dynamiques dans les Décodeurs d'Adresse de Mémoire SRAM, Journées Nationales du Réseau Doctoral de Microélectronique, pp.4-6, 2004. ,
Dynamic Fault Detection in SRAM Pre-Charge Circuits, pp.1-5, 2005. ,
New Test Methodologies for Embedded and Stacked Flash Memories, pp.1-5, 2005. ,
Peak Power Consumption During Scan Testing: Issue, Analysis and Heuristic Solutions, pp.1-5, 2005. ,
DOI : 10.1109/dtis.2006.1708693
State-of-the-Art of Diagnosis Solutions in Scan Environment, pp.1-5, 2005. ,
Analyse des Fautes Dynamiques dans les Circuits de Précharge des Mémoires SRAM, 2005. ,
Incidence des Défauts Résistifs dans les Circuits de Précharge des Mémoires SRAM, JNRDM'05: VIII Journées Nationales du Réseau Doctoral de Microélectronique, pp.10-12, 2005. ,
Analyse et Réduction de la Puissance de Pic Durant le Test Série, Landrault JNRDM'05: VIII Journées Nationales du Réseau Doctoral de Microélectronique, pp.10-12, 2005. ,
Structural-Based Power-Aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing, 2006 IFIP International Conference on Very Large Scale Integration, pp.27-31, 2006. ,
DOI : 10.1109/VLSISOC.2006.313222
URL : https://hal.archives-ouvertes.fr/lirmm-00108141
Test of Dynamic Faults in SRAM Memories, pp.27-31, 2006. ,
URL : https://hal.archives-ouvertes.fr/tel-00341677
Unified Diagnostic Method Focusing Several Fault Models, pp.27-31, 2006. ,
Réduction de la consommation de Puissance de Pic Pendant le Test Série, 2006. ,
Méthode unifiée de diagnostic ciblant l'ensemble des modèles de fautes, Virazel JNRDM'06: IXI Journées Nationales du Réseau Doctoral de Microélectronique, pp.10-12, 2006. ,
Structural Power-Aware Assignment of Xs for Peak Power Reduction during Scan Testing, European Test Symposium, pp.21-25, 2006. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00134781
Failure Mechanisms due to Process Variations in Nanoscale SRAM Core-Cells, European Test Symposium, pp.21-25, 2006. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00134787
Unified Diagnostic Method Targeting Several Fault Models, Virazel VLSIsoc'06: PhD Forum at IFIP International Conference on Very Large Scale Integration, pp.16-18, 2006. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00136869
Diagnostic Multi-Modèles des Circuits Logiques, Virazel MAJECSTIC'06: Manifestation des Jeunes Chercheurs STIC, pp.22-24, 2006. ,
Test and Testability of Redundant Circuits, pp.27-28, 2007. ,
A comprehensive diagnosis methodology targeting several fault models, South European Test Seminar, pp.27-28, 2007. ,
Impact of threshold voltage deviation in SRAM Core-Cells" A, South European Test Seminar, pp.27-28, 2007. ,
Test des Mémoires Flash Embarquées : Analyse de la perturbation entre cellules FloTOx voisines durant une phase de programmation, Daga JNRDM'07: Journées Nationales du Réseau Doctoral de Microélectronique, pp.14-16, 2007. ,
Test et testabilité de structures numériques tolérantes aux fautes, pp.13-15, 2007. ,
Resistive-Open Defect Influences in SRAM I/O Circuitry, pp.13-15, 2007. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00194282
Méthode de diagnostic unifiée pour circuits intégrés numériques, pp.13-15, 2007. ,
Yield Improvement, Fault-Tolerance to the Rescue?, 2008 14th IEEE International On-Line Testing Symposium, pp.18-22, 2008. ,
DOI : 10.1109/IOLTS.2008.10
URL : https://hal.archives-ouvertes.fr/lirmm-00303400
08: Journées des Doctorants de l'Ecole Doctorale I2SUtilisation de structures tolérantes aux fautes pour augmenter le rendementTolérer Plus pour Fabriquer Plus, Virazel JNRDM'08: Journées Nationales du Réseau Doctoral de Microélectronique. Virazel GDR SOC-SIP'08: Colloque GDR SoC-SiP, pp.4-6, 2008. ,
A History-Based Technique for Faults Diagnosis in SRAMs, pp.4-6, 2008. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00341821
Analysis of Resistive-Bridging Defects in SRAM Core-Cell: Impact within the Core-Cell and in the Memory Array, European Test Symposium, pp.25-29, 2009. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00433796
A Logic Diagnosis Approach for Sequential Circuits, European Test Symposium, pp.25-29, 2009. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00433792
SoC Yield Improvement for Future Nanoscale, European Test Symposium, pp.25-29, 2009. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00433798
Trade-off between Power Dissipation and Delay Fault Coverage for LOS and LOC Testing Schemes, Wen LPonTR'09: 2nd International Workshop on Impact of Low-Power design on Test and Reliability, pp.29-2009 ,
DOI : 10.1109/ddecs.2010.5491748
URL : https://hal.archives-ouvertes.fr/lirmm-00435005
Trade-off between Power Dissipation and Delay Fault Coverage For LOS and LOC Testing Schemes, pp.10-12, 2009. ,
DOI : 10.1109/ddecs.2010.5491748
URL : https://hal.archives-ouvertes.fr/lirmm-00435005
Setting Test Conditions for Detecting Faults Induced by Random Dopant Fluctuation in SRAM Core-Cells, Badereddine VARI'10: European Workshop on CMOS Variability, pp.26-27, 2010. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00553626
Power reduction through X-filling of transition fault test vectors for LOS testing, 2011 6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), pp.27-28, 2010. ,
DOI : 10.1109/DTIS.2011.5941434
URL : https://hal.archives-ouvertes.fr/lirmm-00647760
Analysis and Fault Modeling of Actual Resistive Defects in Flash Memories, Pravossoudovitch JNRDM'10: Journées Nationales du Réseau Doctoral de Microélectronique, pp.7-9, 2010. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00553935
Analyse et modélisation des défauts résistifs affectant les mémoires Flash, pp.9-11, 2010. ,
Test Relaxation and X-filling to Reduce Peak Power During At-Speed LOS Testing, pp.9-11, 2010. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00553989
Tolérance aux Fautes et Rendement de Fabrication, pp.9-11, 2010. ,
Robustness Improvement of Digital Circuits A New Hybrid Fault Tolerant Architecture, Wunderlich JNRDM'11: Journées Nationales du Réseau Doctoral de Microélectronique, pp.23-25, 2011. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00679509
A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits, 2011 Asian Test Symposium, pp.15-17, 2011. ,
DOI : 10.1109/ATS.2011.89
URL : https://hal.archives-ouvertes.fr/lirmm-00679513
Test and Reliability of Magnetic Random Access Memories, pp.15-17, 2011. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00679516
Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling, 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp.15-17, 2011. ,
DOI : 10.1109/DDECS.2011.5783110
URL : https://hal.archives-ouvertes.fr/lirmm-00679522
Variability Analysis of an SRAM Test Chip ,
URL : https://hal.archives-ouvertes.fr/lirmm-00651791
Simultaneous Power and Thermal Integrity Analysis for 3D Integrated Systems, Virazel LPonTR'2011 : IEEE International Workshop on Impact of Low-Power design on Test and Reliability European Test Symposium, pp.26-27, 2011. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00651802
Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme, Ahmed LPonTR'2011 : IEEE International Workshop on Impact of Low-Power design on Test and Reliability, pp.26-27, 2011. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00651905
A Robust Infrastructure for Data Collection and Transfer for a Distributed SRAM-based Neutron Detection Platform, Pravossoudovitch, A. Virazel DDT'2011 : 1st Workshop on Dependability Issues in Deep-submicron Technologies, pp.26-27, 2011. ,
Analysis of Resistive-Open Defects in TAS-MRAM Array, Mackay ITC'11: International Test Conference, pp.18-23, 2011. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00679524
Electro-Thermal Analysis of 3D Power Delivery Networks, Virazel DAC'12 : Design Automation Conference, Work-In-Progress Session, pp.3-7, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806836
Defect Localization Through an Effect-Cause based Intra-Cell Diagnosis, pp.13-15, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806841
Impacts of Resistive-Open Defects in the Word-Line Selection of TAS-MRAMs, pp.13-15, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806842
Through-Silicon-Via resistive-open defect analysis, 2012 17TH IEEE EUROPEAN TEST SYMPOSIUM (ETS), pp.13-15, 2012. ,
DOI : 10.1109/ETS.2012.6233037
URL : https://hal.archives-ouvertes.fr/lirmm-00806848
Adaptive Voltage Scaling via Effective On-Chip Timing Uncertainty Measurements, pp.13-15, 2012. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806859
Dynamic Mode Testing of SRAMS under Neutron Radiation, pp.13-15, 2012. ,
DOI : 10.1109/tns.2013.2239311
URL : https://hal.archives-ouvertes.fr/lirmm-00807053
Improving Defect Localization Accuracy by means of Effect-Cause Intra-Cell Diagnosis at Transistor Level, International Workshop on Silicon Debug and Diagnosis, vol.12, pp.8-9 ,
URL : https://hal.archives-ouvertes.fr/lirmm-00806872
Performance Evaluation of Capacitive defects on TAS-MRAMs, pp.10-12, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00839093
Investigating Multiple-Cell-Upsets on a 90mn SRAM, pp.10-12, 2013. ,
DOI : 10.1109/radecs.2013.6937429
URL : https://hal.archives-ouvertes.fr/lirmm-00839108
Fault-Effect Propagation Based Intra-cell Scan Chain Diagnosis, pp.10-12, 2013. ,
URL : https://hal.archives-ouvertes.fr/lirmm-00839113
A Fault-tolerant Architecture for Pipelined Microprocessor Cores, pp.11-13, 2014. ,
DOI : 10.1109/ets.2015.7138733
A Comprehensive Evaluation of Functional Programs for Power-Aware Test, 2014 IEEE 23rd North Atlantic Test Workshop, pp.11-13, 2014. ,
DOI : 10.1109/NATW.2014.23
URL : https://hal.archives-ouvertes.fr/lirmm-01248597
Crosstalk and Supply Noise -Aware Pattern Generation for Delay Testing, pp.11-13, 2014. ,
Analysis of Dynamic Faults in Embedded-SRAMs: Implications for Memory Test, Thème : Test de Mémoires, pp.169-179 ,
DOI : 10.1007/s10836-005-6146-1
URL : https://hal.archives-ouvertes.fr/lirmm-00105313
A SPICE-Like 2T-FLOTOX Core-Cell Model for Defect Injection and Faulty Behavior Prediction in eFlash, Journal of Electronic Testing, vol.3, issue.2-3, pp.127-144 ,
DOI : 10.1007/s10836-008-5096-9
A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.22, issue.11, 2013. ,
DOI : 10.1109/TVLSI.2013.2294080
URL : https://hal.archives-ouvertes.fr/lirmm-01248578
Is TMR Suitable for Yield Improvement, Thème : Tolérance aux Fautes Virazel IET Computers and Digital Techniques, pp.581-592 ,
DOI : 10.1049/iet-cdt.2008.0127
URL : https://hal.archives-ouvertes.fr/lirmm-00406961
Analysis of Deceptive Destructive Read Memory Fault Model and Recommended Testing, IEEE North Atlantic Test Workshop, 1996. ,
False write through and un-restored write electrical level fault models for SRAMs, Proceedings. International Workshop on Memory Technology, Design and Testing (Cat. NO.97TB100159), pp.27-32, 1997. ,
DOI : 10.1109/MTDT.1997.619391
Static and dynamic behavior of memory cell array opens and shorts in embedded DRAMs, Proceedings Design, Automation and Test in Europe. Conference and Exhibition 2001, pp.496-503, 2001. ,
DOI : 10.1109/DATE.2001.915069
Defect-based delay testing of resistive vias-contacts a critical evaluation, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.467-476, 1999. ,
DOI : 10.1109/TEST.1999.805769
March iC-: An Improved Version of March C- for ADOFs Detection, 22nd IEEE VLSI Test Symposium, 2004. Proceedings., pp.129-134, 2004. ,
DOI : 10.1109/VTEST.2004.1299236
URL : https://hal.archives-ouvertes.fr/lirmm-00108772
March Tests Improvement for Address Decoder Open and Resistive Open Fault Detection, Proc ,
Dynamic read destructive fault in embedded-SRAMs: analysis and march test solution, Proceedings. Ninth IEEE European Test Symposium, 2004. ETS 2004., 2004. ,
DOI : 10.1109/ETSYM.2004.1347645
Using march tests to test SRAMs, IEEE Design & Test of Computers, vol.10, issue.1, pp.8-14, 1993. ,
DOI : 10.1109/54.199799
Testing Semiconductor Memories, Theory and Practice, Gouda, The Netherlands, 1998. ,
Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-289, 2000. ,
DOI : 10.1109/VTEST.2000.843856
Industrial Evaluation of DRAM Tests, Proc. Design Automation and Test in Europe, pp.623-630, 1999. ,
Testing static and dynamic faults in random access memories, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002), pp.395-400, 2002. ,
DOI : 10.1109/VTS.2002.1011170
Testing for Resistive Opens and Stuck Opens, Proc. Int'l Test Conf, pp.1049-1058, 2001. ,
Simple and Efficient Algorithms for Functional RAM Testing, Proc. Int'l Test Conf, pp.236-239, 1982. ,
High volume microprocessor test escapes, an analysis of defects our tests are missing, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.25-34, 1998. ,
DOI : 10.1109/TEST.1998.743133
Integration of Non-classical Faults in Standard March Tests Records of the IEEE Int, Memory Technology, Design and Testing, pp.91-96, 1998. ,
Detection of CMOS address decoder open faults with March and pseudo random memory tests, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270), pp.53-62, 1998. ,
DOI : 10.1109/TEST.1998.743137
Resistance Characterization of Interconnect Weak and Strong Open Defects, IEEE Design & Test of Computers, vol.19, issue.5, pp.18-26, 2002. ,
Test and testability techniques for open defects in RAM address decoders, Proceedings ED&TC European Design and Test Conference, pp.428-434, 1996. ,
DOI : 10.1109/EDTC.1996.494336
Open defects in CMOS RAM address decoders, IEEE Design & Test of Computers, vol.14, issue.2, pp.26-33, 1997. ,
DOI : 10.1109/54.587738
Industrial evaluation of stress combinations for march tests applied to SRAMs, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034), pp.983-992, 1999. ,
DOI : 10.1109/TEST.1999.805831
Defect analysis and realistic fault model extensions for static random access memories, Records of the IEEE International Workshop on Memory Technology, Design and Testing, pp.119-124, 2000. ,
DOI : 10.1109/MTDT.2000.868625
Reliability issues of flash memory cells, Proceedings of the IEEE, vol.81, issue.5, pp.776-788, 1993. ,
DOI : 10.1109/5.220908
On-chip high-voltage generation in NMOS integrated circuits using an improved voltage multiplier technique, 1976. ,
DOI : 10.1109/jssc.1976.1050739
An Overview of Failure Mechanisms in Embedded Flash Memories, 24th IEEE VLSI Test Symposium, pp.108-113, 2006. ,
DOI : 10.1109/VTS.2006.19
URL : https://hal.archives-ouvertes.fr/lirmm-00102761
Retention and Reliability Problems in Embedded Flash Memories: Analysis and Test of Defective 2T-FLOTOX Tunnel Window, 25th IEEE VLSI Test Symmposium (VTS'07), pp.47-52, 2007. ,
DOI : 10.1109/VTS.2007.52
URL : https://hal.archives-ouvertes.fr/lirmm-00151034
A realistic fault model for flash memories, Proc IEEE Asian Test Symposium, pp.274-281, 2000. ,
VLSI memory chip design, 2001. ,
DOI : 10.1007/978-3-662-04478-0
A simple Flash memory cell model for transient circuit simulation, IEEE Electron Device Letters, vol.26, issue.8, pp.563-565, 2005. ,
DOI : 10.1109/LED.2005.852525
Flash memory disturbances: modeling and test, Proceedings 19th IEEE VLSI Test Symposium. VTS 2001, pp.218-224, 2001. ,
DOI : 10.1109/VTS.2001.923442
Simulating program disturb faults in flash memories using spice compatible electrical model, Proc IEEE International ASIC/ SOC Conference, pp.2286-2291, 2000. ,
DOI : 10.1109/TED.2003.816546
Flash memory cells? an overview Floating-gate EEPROM cell model based on MOS model 9, Proc IEEE Portal JM IEEE Int Symp Circuits Syst, vol.85, issue.3, pp.1248-1271799, 1997. ,
Semiconductor memories: technology, testing and reliability, 1997. ,
DOI : 10.1109/9780470546406
He is presently an Associate Professor at the University of Marseille, and works in the Micro and Nano-electronics Department of the IM2NP (Institute of Materials, Microelectronics and Nanosciences of Provence, France) His research interests include the various aspects of design, diagnostic and test of memories with special emphasis on emergent non-volatile memories, Sc. in Electrical Engineering from Polytech Montpellier, and obtained the PhD degree in Microelectronics from the University of Montpellier, 1980. ,
Daga is in charge of the embedded non volatile memory group, at ATMEL's central engineering team His research interests involve the development of embedded non volatile memories, including design for test and reliability aspects. Daga has a PhD in electronics from Montpellier University, France. He is the author and co-author of more than 40 papers ,
He is currently Research Director at CNRS (French National Center for Scientific Research), and works in the Microelectronics Department of the LIRMM (Laboratory of Informatics Robotics and Microelectronics of Montpellier?France ) Patrick Girard is the Vice-Chair of the European Test Technology Technical Council (ETTTC) of the IEEE Computer Society He has served as technical program committee member of the ACM He has served as Test Track Chair for DAC He has also served as Program Chair for, Electrical Engineering and a Ph.D. degree in Microelectronics from the University He is the Editor-in-Chief of the ASP Journal of Low Power Electronics (JOLPE) and an Associate Editor of the IEEE Transactions on Computers and the Journal of Electronic Testing?Theory and Applications IFIP International Conference on VLSI-SOC, IEEE VLSI Test Symposium (VTS), IEEE European Test Symposium (ETS), IEEE International On-Line Testing Symposium (IOLTS), IEEE Asian Test Symposium (ATS), ACM/ IEEE International Symposium on Low Power Electronic Design (ISLPED), IEEE International Symposium on Electronic Design, Test & Applications (DELTA) and IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS) + NanoTEST) and has managed industrial research contracts with major companies like Infineon Technologies His research interests include the REFERENCES [1] International Technology Roadmap for Semiconductors (ITRS), Semiconductor Industry Association, 1988. ,
Evaluation, validation and design of hybrid CMOS?Nonvolatile emerging technology cells for dynamically reconfigurable fine grain architecture, 2007. ,
Testing MRAM for Write Disturbance Fault, 2006 IEEE International Test Conference, pp.277-288, 2006. ,
DOI : 10.1109/TEST.2006.297702
Write Disturbance Modeling and Testing for MRAM, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.16, issue.3, pp.277-288, 2008. ,
DOI : 10.1109/TVLSI.2007.915402
Diagnosis of MRAM Write Disturbance Fault, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.18, issue.12, pp.1762-1766, 2010. ,
DOI : 10.1109/TVLSI.2009.2026905
MRAM defect analysis and fault modeling, Proc. Int. Test Conf, pp.124-133, 2004. ,
Impact of resistive-open defects on the heat current of TAS-MRAM architectures, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), pp.532-537, 2012. ,
DOI : 10.1109/DATE.2012.6176526
URL : https://hal.archives-ouvertes.fr/lirmm-00689024
Functional memory faults: a formal notation and a taxonomy, Proceedings 18th IEEE VLSI Test Symposium, pp.281-286, 2000. ,
DOI : 10.1109/VTEST.2000.843856
The Stoner???Wohlfarth model of ferromagnetism, European Journal of Physics, vol.29, issue.3, pp.475-487, 2008. ,
DOI : 10.1088/0143-0807/29/3/008
Design considerations for MRAM, IBM Journal of Research and Development, vol.50, issue.1, pp.25-39, 2006. ,
DOI : 10.1147/rd.501.0025
Method of writing to scalable magnetoresistance random access memory element, U.S. Patent, vol.6, pp.545-906, 2003. ,
Dynamic compact model of thermally assisted switching magnetic tunnel junctions, Journal of Applied Physics, vol.106, issue.12, pp.123906-123907, 2009. ,
DOI : 10.1063/1.3259373
Current-driven excitation of magnetic multilayers, Journal of Magnetism and Magnetic Materials, vol.159, issue.1-2, pp.1-7, 1996. ,
DOI : 10.1016/0304-8853(96)00062-5
Writeoptimized reliable design of STT MRAM, Proc. IEEE ISLPED, pp.3-8, 2012. ,
DOI : 10.1145/2333660.2333664
Small Delay Fault Model for Intra-Gate Resistive Open Defects, 2009 27th IEEE VLSI Test Symposium, pp.27-32, 2009. ,
DOI : 10.1109/VTS.2009.25
Using TMR architectures for yield improvement ,
Bilateral testing of nano-scale fault tolerant circuits, Proc. IEEE Defect and Fault Tolerance in VLSI Systems, pp.309-317, 2006. ,
Design for testability and test generation for static redundancy system level fault tolerant circuits, Proc. IEEE Int. Test Conf, pp.812-818, 1989. ,
New high speed CMOS self-checking voter, Proc. IEEE Int. On-Line Testing Symp, pp.58-63, 2004. ,
Yield improvement, fault-tolerance to the rescue, Proc. IEEE Int. On-Line Testing Symp, pp.157-165, 2008. ,
Are defecttolerant circuits with redundancy really cost effective? Complete and realistic cost model, Proc. IEEE Defect and Fault Tolerance in VLSI Systems, pp.157-165, 1997. ,
Integrated circuit manufacturabilityMultilevel hypergraph partitioning: applications in VLSI domain, IEEE Trans. VLSI Syst, issue.71, pp.69-79, 1999. ,