High power consumption is a key factor hindering System-on-Chip (SoC) performance. Accurate and efficient power models have to be introduced early in the design flow, when most of the optimization potential is possible to be obtained. However, early accuracy cannot be ensured because of the lack of precise knowledge of the circuit structure. Current SoC design paradigm relies on Intellectual Property (IP) reuse, as low-level information about circuit components and structure is available. Thus, estimation accuracy at system level may be improved by using this information and developing an estimation methodology that fits IP power modeling needs. This paper presents a Hybrid Power Estimation Technique (HPET). It is based on an effective library characterization methodology and an efficient hybrid power modeling approach to accurately and quickly assess gate-level power consumption. The aim is to provide valuable and accurate physical information so appropriate optimization techniques are implemented. Our approach can be used to compute both realistic instantaneous and average power in a single simulation. We performed experiments on different benchmark circuits synthesized using 28 nm FDSOI technology. We compared our approach with SPECTRE and PrimeTime-PX simulations. Experimental results showed that we can achieve up to 68× speedup with a mean error close to 7% and 10% for the instantaneous and average power respectively. This demonstrates that HPET is an effective technique to enhance power estimation early in the design flow.