Skip to Main content Skip to Navigation



 Test and dEpendability of microelectronic integrated SysTems

Consult your copyright


Consulter la politique des éditeurs également sur

Number of Files


Nomber of Notices


Collaborations’ map


Test and Security ZigBee Power demand Single event upset SEU Power supplies Logic gates Testing Diagnosis Circuit faults Laser Particle detector Scan Attacks Countermeasure Integrated circuit testing Integrated circuits Alternate testing Fault attacks Machine Learning OQPSK Transistors Soft errors Integrated circuit reliability Neutrons Ensemble methods Diffusion model Integrated circuit design Indirect testing Digital ATE Process variability Radiation hardening Integrated circuit modeling FDSOI Computer architecture One bit acquisition COTS 3D integration Hardware Security Security Transient faults Software Fiabilité Switches Analytical models Fault tolerant systems Simulation Machine-learning algorithms RF test 1-bit acquisition Power consumption Approximate Computing Multiple cell upset MCU Libraries Approximate computing Hardware Trojan Hardware Fault injection Random access memory SER BIST Stream Cipher Fault tolerance Education Phase noise Context Saving Through-silicon vias Radiation Digital signal processing Estimation Transient analysis Atmospheric neutrons Scan Encryption Cross section RF integrated circuits Test efficiency Heavy ions Protons Logic testing Clocks Memories SEU Test Reliability Monitoring Fault simulation Fault Injection JTAG Computational modeling Noise measurement Microprocessors ATPG Combinational circuits Automatic test pattern generation Test cost reduction Flip-flops Analog/RF integrated circuits Delays SRAM Analog signals Soft error Hardware security Microprocessor chips