Test and dEpendability of microelectronic integrated SysTems

Consult your copyright


Consulter la politique des éditeurs également sur

Number of Files


Nomber of Notices

Collaborations’ map


Digital signal processing Analog signals Estimation Microprocessors Logic gates Education Hardware Trojans Hardware security Hardware Security Soft errors COTS Software Delays Fault Injection Laser Power demand Encryption FRAM Particle detector Diagnosis Dynamic test ATPG Integrated circuits Multiple cell upset MCU Diffusion model Fault injection Digital ATE Microprocessor chips 1-bit acquisition Protons Test and Security BIST Heavy ions Monitoring Security Reliability Hardware Power consumption Scan Attacks Countermeasure Computational modeling 3D integration Databases Transistors Atmospheric neutrons SRAM FDSOI Test Power supplies Switches Integrated circuit modeling Alternate testing Memories Logic testing Test cost reduction Indirect testing Fault simulation Scan Encryption Single event upset SEU Integrated circuit testing Hardware Trojan Clocks Circuit faults One bit acquisition Integrated circuit reliability Process variability Phase noise FDSOI Technology Transient faults SEU Radiation Heating Functional and Structural test Through-silicon vias Test efficiency Libraries Stream Cipher Noise measurement Flip-flops Fiabilité Design for testability Data retention Fault attacks Fault diagnosis FDSOI technology Evaluation Analog/RF integrated circuits Computer architecture Simulation Hardware Trojan Detection Fault tolerance Testing Random access memory Transient analysis SER Approximate computing Fault tolerant systems Cross section Dependability Integrated circuit design Automatic test pattern generation