Skip to Main content Skip to Navigation
New interface



 Test and dEpendability of microelectronic integrated SysTems

Consult your copyright

Number of Files


Nomber of Notices


Collaborations’ map


Fault Tolerance Neutrons Education JTAG Test confidence COTS Software Memories BIST Transistors Noise measurement Analog/RF integrated circuits Light Encryption One bit acquisition Dependability Multiple cell upset MCU Logic gates Digital ATE EVM measurement Diagnosis Hardware Clocks 3D integration Hardware security Memory Approximate Computing Computer architecture Test CMOS Automatic test pattern generation Integrated circuit modeling Integrated circuit testing Integrated circuit reliability OQPSK Silicon Radiation effects Single event upset SEU Dynamic test Radiation Power demand Indirect test ATPG RISC-V Test cost reduction Laser Alternate testing Fault tolerance Machine-learning algorithms FDSOI Circuit faults ZigBee Latch design Customer returns Power supplies Analog signals Laser fault injection Test and Security Integrated circuits SEU Design-for-Trust Test efficiency Functional approximation Fault-tolerance Ensemble methods Scan Encryption Radiation hardening Integrated circuit noise Fault Injection Circuit reliability Combinational circuits Stream Cipher Microprocessors Switches Fault injection 1-bit acquisition Soft error SEE Intra-cell defects Digital modulation Machine Learning IoT Security Phase noise Context saving Approximate computing Low-cost measurements RF integrated circuits Evaluation Functional test Double-node upset Data retention Delays Reliability Indirect testing Flash memory Scan Attacks Countermeasure SRAM Testing Digital signal processing RF test