Supply Voltage Glitches Effects on CMOS Circuits

Abstract : Among the attacks applied on secure circuits, fault injection techniques consist in the use of a combination of environmental conditions that induce computational errors in the chip that can leak protected informations. The purpose of our study is to build an accurate model able to describe the behaviour of CMOS circuits in presence of deliberated short supply voltage variations. This behaviour depends strongly on the basic gates (combinational logic, registers. . . ) that make up the circuit. In this paper, we show why D-flip-flop are resistant to power supply glitches occurring between clock transitions and we propose an approach to evaluate the basic elements sensitivities towards faults generated by power glitches. Our aimed model will consequently be dependent on this sensitivity.
Type de document :
Communication dans un congrès
IEEE. DTIS'06: Design and Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis (Tunisia), pp.257-261, 2006
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Soumis le : mercredi 13 septembre 2006 - 11:52:18
Dernière modification le : jeudi 11 janvier 2018 - 06:14:31
Document(s) archivé(s) le : lundi 5 avril 2010 - 23:40:18

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  • HAL Id : lirmm-00093365, version 1

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Anissa Djellid-Ouar, Guy Cathébras, Frédéric Bancel. Supply Voltage Glitches Effects on CMOS Circuits. IEEE. DTIS'06: Design and Test of Integrated Systems in Nanoscale Technology, Sep 2006, Tunis (Tunisia), pp.257-261, 2006. 〈lirmm-00093365〉

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