Secure Scan Techniques: a Comparison

David Hély 1 Frédéric Bancel 1 Marie-Lise Flottes 2 Bruno Rouzeyre 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : Designing secure ICs requires fulfilling many design rules in order to protect access to secret data. However, these security design requirements may be in opposition to test needs and testability improvement techniques that increase both observability and controllability. Nevertheless, secure chip designers cannot neglect the testability of their chip; a high quality production testing is primordial to ensure a good level of security since any faulty devices could induce major security vulnerability. In this paper, we present different techniques securing the scan chain technique and compare them to point out their pros and cons.
Type de document :
Communication dans un congrès
IOLTS'06: 12th International On-Line Testing Symposium, Jul 2006, Como, Italy, IEEE, pp.119-124, 2006, 〈10.1109/IOLTS.2006.55〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00102857
Contributeur : Christine Carvalho de Matos <>
Soumis le : lundi 2 octobre 2006 - 17:03:07
Dernière modification le : jeudi 11 janvier 2018 - 06:27:18

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David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre. Secure Scan Techniques: a Comparison. IOLTS'06: 12th International On-Line Testing Symposium, Jul 2006, Como, Italy, IEEE, pp.119-124, 2006, 〈10.1109/IOLTS.2006.55〉. 〈lirmm-00102857〉

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