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Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing

Patrick Girard 1 Yannick Bonhomme 2
1 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00105357
Contributor : Christine Carvalho de Matos <>
Submitted on : Wednesday, October 11, 2006 - 7:51:31 AM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM

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  • HAL Id : lirmm-00105357, version 1

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CNRS | SYSMIC | LIRMM | LIRMM_MIC | MIC | MIPS | UNIV-MONTPELLIER

Citation

Patrick Girard, Yannick Bonhomme. Low Power Scan Chain Design: A Solution for an Efficient Tradeoff Between Test Power and Scan Routing. Journal of Low Power Electronics, American Scientific Publishers, 2005, 1 (1), pp.85-95. ⟨lirmm-00105357⟩

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