Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays

Abstract : The test of field programmable analog arrays (FPAA) may be performed based on partitioning these devices in three main parts: I/O cells, interconnection networks and configurable analog blocks. In this work, a scheme for testing the I/O cells and the local and global interconnection networks of FPAAs is proposed, using an adjacency graph model to represent the programmable interconnection and I/O resources, and then devising a set of test configurations (TC) by solving graph coloring problems. The goal is to achieve a near minimum number of TCs ensuring all stuck-open and stuck-on faults in switches, as well as opens and shorts in wires, are covered. Large parametric faults in interconnects are implicitly covered in these TCs by judiciously choosing test stimuli and, in I/O buffers, by means of an oscillation-based test strategy.
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VTS: VLSI Test Symposium, May 2005, Palm Springs, CA, United States. 23rd IEEE VLSI Test Symposium, pp.389-400, 2005, 〈10.1109/VTS.2005.85〉
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00105998
Contributeur : Christine Carvalho de Matos <>
Soumis le : vendredi 13 octobre 2006 - 10:22:45
Dernière modification le : jeudi 24 mai 2018 - 15:59:24

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Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, et al.. Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS: VLSI Test Symposium, May 2005, Palm Springs, CA, United States. 23rd IEEE VLSI Test Symposium, pp.389-400, 2005, 〈10.1109/VTS.2005.85〉. 〈lirmm-00105998〉

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