Skip to Main content Skip to Navigation
Conference papers

Speed Indicators for Circuit Optimization

Abstract : Due to the development of high performance portable applications associated to the high-density integration allowed by deep submicron processes, circuit optimization under delay constraints has emerged as a critical issue for VLSI designers. The objective of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths [1], to circuit sizing in order to solve the circuit convergence branch problem. We propose a coefficient based approach to solve the divergence branch problem. Validation is given by comparing with an industrial tool the performance of different benchmarks implemented in a standard 180nm CMOS process.
Complete list of metadatas

Cited literature [11 references]  Display  Hide  Download

https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106076
Contributor : Christine Carvalho de Matos <>
Submitted on : Friday, September 13, 2019 - 3:26:26 PM
Last modification on : Friday, September 13, 2019 - 3:31:18 PM
Long-term archiving on: : Saturday, February 8, 2020 - 12:00:35 PM

File

ark__67375_HCB-2DXVSWH1-8.pdf
Publisher files allowed on an open archive

Identifiers

Collections

Citation

Alexandre Verle, Alexis Landrault, Philippe Maurine, Nadine Azemard. Speed Indicators for Circuit Optimization. PATMOS: Power And Timing Modeling, Optimization and Simulation, Sep 2005, Leuven, Belgium. pp.618-628, ⟨10.1007/11556930_63⟩. ⟨lirmm-00106076⟩

Share

Metrics

Record views

130

Files downloads

55