This paper addresses the problem of circuit performance optimization that is a complete task to realize in the last step of the I.C. design flow. The goal of this work is to avoid the use of random mathematical methods (very CPU time expensive), by defining simple, fast and deterministic indicators allowing easy and fast implementation of circuits at the required speed. We propose to extend the method of equal sensitivity, previously developed for combinatorial paths, to combinatorial circuit sizing in order to solve the convergence branch problem. We also propose a coefficient based approach to solve the divergence branch problem. Validations are given by comparing the performance of different benchmarks obtained with our protocol and with an industrial tool in a standard 180 nm CMOS process.