Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Benoit Lasbouygues 1 Robin Wilson 1 Nadine Azemard 2 Philippe Maurine 2
2 SysMIC - Conception et Test de Systèmes MICroélectroniques
LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier
Abstract : In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of numerous new factors that impose a drastic change in validation and physical verification methods. One of these major on going changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the path delay considering the operating conditions of each cell.
Type de document :
Communication dans un congrès
TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.28-34, 2006
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00106705
Contributeur : Martine Peridier <>
Soumis le : lundi 16 octobre 2006 - 09:51:43
Dernière modification le : lundi 16 juillet 2018 - 11:08:13

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  • HAL Id : lirmm-00106705, version 1

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Benoit Lasbouygues, Robin Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Voltage Drops and Temperature Gradients. TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp.28-34, 2006. 〈lirmm-00106705〉

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