Timing Analysis in Presence of Voltage Drops and Temperature Gradients - LIRMM - Laboratoire d’Informatique, de Robotique et de Microélectronique de Montpellier Access content directly
Conference Papers Year : 2006

Timing Analysis in Presence of Voltage Drops and Temperature Gradients

Abstract

In the nanometer era, the physical verification of CMOS digital circuit becomes a complex task. Designers must account of numerous new factors that impose a drastic change in validation and physical verification methods. One of these major on going changes in timing verification to handle process variation lies in the progressive development of statistical static timing engines. However the statistical approach cannot capture accurately the deterministic variations of both the voltage and temperature variations. Therefore, we define a novel method, based on non-linear derating coefficients, to account of these environmental variations. Based on temperature and voltage drop CAD tool reports, this method allows computing the path delay considering the operating conditions of each cell.
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Dates and versions

lirmm-00106705 , version 1 (16-10-2006)

Identifiers

  • HAL Id : lirmm-00106705 , version 1

Cite

Benoit Lasbouygues, Robin M. Wilson, Nadine Azemard, Philippe Maurine. Timing Analysis in Presence of Voltage Drops and Temperature Gradients. TAU: Timing Issues in the Specification and Synthesis of Digital Systems, Feb 2006, San Jose, CA, United States. pp.28-34. ⟨lirmm-00106705⟩
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