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Conference papers
BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs
Abstract : In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.
Cited literature [20 references]
https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108824
Contributor : Christine Carvalho de Matos <>
Submitted on : Monday, October 23, 2006 - 12:56:25 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:39:32 PM
Contributor : Christine Carvalho de Matos <>
Submitted on : Monday, October 23, 2006 - 12:56:25 PM
Last modification on : Friday, November 27, 2020 - 6:04:03 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:39:32 PM