BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

Abstract : In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.
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Communication dans un congrès
IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. IEEE Computer Society, 10th IEEE International Symposium on On-Line Testing and Robust System Design, pp.187-192, 2004, 〈10.1109/OLT.2004.1319686〉
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Contributeur : Christine Carvalho de Matos <>
Soumis le : lundi 23 octobre 2006 - 12:56:25
Dernière modification le : jeudi 7 février 2019 - 14:43:30
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Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. IEEE Computer Society, 10th IEEE International Symposium on On-Line Testing and Robust System Design, pp.187-192, 2004, 〈10.1109/OLT.2004.1319686〉. 〈lirmm-00108824〉

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