BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

Patrick Girard; Olivier Héron; Serge Pravossoudovitch; Michel Renovell

doi:10.1109/OLT.2004.1319686

Conference papers

BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

Patrick Girard ¹ Olivier Héron ² Serge Pravossoudovitch ¹ Michel Renovell ¹

1 SysMIC - Conception et Test de Systèmes MICroélectroniques

LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

2 LIRMM - Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier

Abstract : In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.

Document type :

Conference papers

Domain :

Engineering Sciences [physics] / Other

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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

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