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BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs

Abstract : In this paper, we propose a BIST scheme for exhaustive testing all delay faults in the logic architecture of symmetrical FPGAs. This scheme is applicable in a manufacturing-oriented test (MOT) context. Our technique enables the detection of delay faults in the logic architecture and consists in chaining the logic cells in a specific way. The test of all the delay faults can be done with a reduced test sequence and does not require expensive ATE. To illustrate its feasibility, this BIST approach has been implemented in a VIRTEX FPGA from XILINX Inc.
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https://hal-lirmm.ccsd.cnrs.fr/lirmm-00108824
Contributor : Christine Carvalho de Matos <>
Submitted on : Monday, October 23, 2006 - 12:56:25 PM
Last modification on : Wednesday, August 28, 2019 - 3:46:02 PM
Long-term archiving on: : Tuesday, April 6, 2010 - 8:39:32 PM

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Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell. BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS: International On-Line Testing Symposium, Jul 2004, Madeira Island, Portugal. pp.187-192, ⟨10.1109/OLT.2004.1319686⟩. ⟨lirmm-00108824⟩

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